OpenFPGA/yosys/manual/APPNOTE_011_Design_Investig.../example_03.dot

12 lines
330 B
Plaintext

digraph "example" {
rankdir="LR";
remincross=true;
v0 [ label="a" ];
v1 [ label="b" ];
v2 [ label="$2_Y" ];
c4 [ shape=record, label="{{<p1> A|<p2> B}|$2\n$add|{<p3> Y}}" ];
v0:e -> c4:p1:w [color="black", label=""];
v1:e -> c4:p2:w [color="black", label=""];
c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""];
}