OpenFPGA/yosys/manual/APPNOTE_011_Design_Investig.../example_01.dot

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digraph "example" {
rankdir="LR";
remincross=true;
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n10 [ shape=octagon, label="y", color="black", fontcolor="black" ];
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x1 [shape=box, style=rounded, label="BUF"];
x2 [shape=box, style=rounded, label="BUF"];
n1 [ shape=diamond, label="$0\\y[1:0]" ];
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c18:p17:e -> n10:w [color="black", style="setlinewidth(3)", label=""];
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c14:p13:e -> c21:p12:w [color="black", style="setlinewidth(3)", label=""];
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c20:p13:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
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x1:e:e -> c20:p19:w [color="black", label=""];
c21:p13:e -> c20:p12:w [color="black", style="setlinewidth(3)", label=""];
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}