OpenFPGA/yosys/manual/APPNOTE_011_Design_Investig.../cmos_00.dot

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digraph "cmos_demo" {
rankdir="LR";
remincross=true;
n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
n6 [ shape=octagon, label="y", color="black", fontcolor="black" ];
c10 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g0\nNOR|{}}" ];
c11 [ shape=record, label="{{<p7> A|<p9> Y}|$g1\nNOT|{}}" ];
c12 [ shape=record, label="{{<p7> A|<p9> Y}|$g2\nNOT|{}}" ];
c13 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g3\nNOR|{}}" ];
x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
x0:e -> c13:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
c14 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g4\nNOR|{}}" ];
x1 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
x1:e -> c14:p8:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
x2 [ shape=record, style=rounded, label="<s0> 0:0 - 0:0 " ];
x2:e -> c14:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
n1 [ shape=diamond, label="$n4" ];
n1:e -> c10:p9:w [color="black", label=""];
n1:e -> c14:p7:w [color="black", label=""];
n2 [ shape=diamond, label="$n5" ];
n2:e -> c11:p9:w [color="black", label=""];
n2:e -> c13:p7:w [color="black", label=""];
n3 [ shape=diamond, label="$n6_1" ];
n3:e -> c12:p9:w [color="black", label=""];
n3:e -> c13:p8:w [color="black", label=""];
n4:e -> c10:p8:w [color="black", label=""];
n4:e -> c12:p7:w [color="black", label=""];
n5:e -> c10:p7:w [color="black", label=""];
n5:e -> c11:p7:w [color="black", label=""];
n6:e -> x0:s0:w [color="black", label=""];
n6:e -> x1:s0:w [color="black", label=""];
n6:e -> x2:s0:w [color="black", label=""];
}