tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM		2021-04-28 10:47:17 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in dual port ram 16k benchmark	2021-04-27 23:33:20 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
openfpga_arch	[Arch] Add example arch using 1-kbit DPRAM	2021-04-28 10:47:17 -06:00
openfpga_cell_library	[HDL] Patch dpram cell	2021-04-27 23:42:31 -06:00
openfpga_shell_scripts	[Script] Enable constant net routing for heterogeneous FPGAs	2021-04-23 20:44:36 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Patch yosys script for 16kbit dual port RAM	2021-04-27 23:41:47 -06:00
regression_test_scripts	[Test] Deploy new test to CI	2021-04-26 16:29:54 -06:00
scripts	[Script] Add tolerance options to check qor script	2021-03-23 12:26:33 -06:00
tasks	[Test] Bug fix in test case for DPRAM whose width = 2	2021-04-28 10:31:22 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Reduce the size of DPRAM in example architecture to accelerate testing	2021-04-28 10:45:10 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00