734 lines
27 KiB
C
Executable File
734 lines
27 KiB
C
Executable File
#include <math.h>
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#include <string.h>
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#include "util.h"
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#include "vpr_types.h"
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#include <assert.h>
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#include "globals.h"
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#include "rr_graph_util.h"
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#include "rr_graph_area.h"
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/* Some useful subroutines in Spice utils*/
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int determine_tree_mux_level(int mux_size);
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int determine_num_input_basis_multilevel_mux(int mux_size, int mux_level);
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/************************ Subroutines local to this module *******************/
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static void count_bidir_routing_transistors(int num_switch, float R_minW_nmos,
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float R_minW_pmos, float sram_area);
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static void count_unidir_routing_transistors(t_segment_inf * segment_inf,
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float R_minW_nmos, float R_minW_pmos, float sram_area);
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static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock,
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int max_inputs_to_cblock, float trans_cblock_to_lblock_buf,
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float trans_sram_bit);
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static float *alloc_and_load_unsharable_switch_trans(int num_switch,
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float trans_sram_bit, float R_minW_nmos);
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static float *alloc_and_load_sharable_switch_trans(int num_switch,
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float trans_sram_bit, float R_minW_nmos, float R_minW_pmos);
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/* mrFPGA: Xifan TANG*/
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//static
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//float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos);
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/*end */
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static float trans_per_mux(int num_inputs, float trans_sram_bit,
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float pass_trans_area, t_switch_inf target_switch);
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static float trans_per_R(float Rtrans, float R_minW_trans);
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/*************************** Subroutine definitions **************************/
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void count_routing_transistors(enum e_directionality directionality,
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int num_switch, t_segment_inf * segment_inf, float R_minW_nmos,
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float R_minW_pmos, float sram_area) {
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/* Counts how many transistors are needed to implement the FPGA routing *
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* resources. Call this only when an rr_graph exists. It does not count *
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* the transistors used in logic blocks, but it counts the transistors in *
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* the input connection block multiplexers and in the output pin drivers and *
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* pass transistors. NB: this routine assumes pass transistors always *
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* generate two edges (one forward, one backward) between two nodes. *
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* Physically, this is what happens -- make sure your rr_graph does it. *
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* *
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* I assume a minimum width transistor takes 1 unit of area. A double-width *
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* transistor takes the twice the diffusion width, but the same spacing, so *
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* I assume it takes 1.5x the area of a minimum-width transitor. */
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if (directionality == BI_DIRECTIONAL) {
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count_bidir_routing_transistors(num_switch, R_minW_nmos, R_minW_pmos, sram_area);
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} else {
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assert(directionality == UNI_DIRECTIONAL);
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count_unidir_routing_transistors(segment_inf, R_minW_nmos, R_minW_pmos, sram_area);
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}
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}
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void count_bidir_routing_transistors(int num_switch, float R_minW_nmos,
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float R_minW_pmos, float sram_area) {
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/* Tri-state buffers are designed as a buffer followed by a pass transistor. *
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* I make Rbuffer = Rpass_transitor = 1/2 Rtri-state_buffer. *
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* I make the pull-up and pull-down sides of the buffer the same strength -- *
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* i.e. I make the p transistor R_minW_pmos / R_minW_nmos wider than the n *
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* transistor. *
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* *
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* I generate two area numbers in this routine: ntrans_sharing and *
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* ntrans_no_sharing. ntrans_sharing exactly reflects what the timing *
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* analyzer, etc. works with -- each switch is a completely self contained *
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* pass transistor or tri-state buffer. In the case of tri-state buffers *
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* this is rather pessimisitic. The inverter chain part of the buffer (as *
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* opposed to the pass transistor + SRAM output part) can be shared by *
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* several switches in the same location. Obviously all the switches from *
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* an OPIN can share one buffer. Also, CHANX and CHANY switches at the same *
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* spot (i,j) on a single segment can share a buffer. For a more realistic *
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* area number I assume all buffered switches from a node that are at the *
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* *same (i,j) location* can share one buffer. Only the lowest resistance *
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* (largest) buffer is implemented. In practice, you might want to build *
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* something that is 1.5x or 2x the largest buffer, so this may be a bit *
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* optimistic (but I still think it's pretty reasonable). */
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int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */
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/* Xifan TANG: cb switches*/
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int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */
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/* END */
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/* corresponding to IPINs will be 0. */
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boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */
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float *shared_buffer_trans; /* [0..max_nx,ny)] */
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float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */
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t_rr_type from_rr_type, to_rr_type;
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int from_node, to_node, iedge, num_edges, maxlen;
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int iswitch, i, j, iseg, max_inputs_to_cblock;
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float input_cblock_trans, shared_opin_buffer_trans;
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const float trans_sram_bit = sram_area;
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/* Two variables below are the accumulator variables that add up all the *
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* transistors in the routing. Make doubles so that they don't stop *
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* incrementing once adding a switch makes a change of less than 1 part in *
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* 10^7 to the total. If this still isn't good enough (adding 1 part in *
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* 10^15 will still be thrown away), compute the transistor count in *
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* "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing *
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* the partial sums together. */
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double ntrans_sharing, ntrans_no_sharing;
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/* Buffers from the routing to the ipin cblock inputs, and from the ipin *
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* cblock outputs to the logic block, respectively. Assume minimum size n *
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* transistors, and ptransistors sized to make the pull-up R = pull-down R. */
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float trans_track_to_cblock_buf;
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float trans_cblock_to_lblock_buf;
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ntrans_sharing = 0.;
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ntrans_no_sharing = 0.;
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max_inputs_to_cblock = 0;
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/* Assume the two buffers below are 4x minimum drive strength (enough to *
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* drive a fanout of up to 16 pretty nicely -- should cover a reasonable *
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* wiring C plus the fanout. */
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trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos,
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R_minW_pmos);
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trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos,
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R_minW_pmos);
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num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int));
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/* Xifan TANG: cb switches*/
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switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int));
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for (i = 0; i < num_rr_nodes; i++) {
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switches_to_cblock[i] = OPEN;
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}
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/* END */
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maxlen = std::max(nx, ny) + 1;
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cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean));
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shared_buffer_trans = (float *) my_calloc(maxlen, sizeof(float));
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unsharable_switch_trans = alloc_and_load_unsharable_switch_trans(num_switch,
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trans_sram_bit, R_minW_nmos);
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sharable_switch_trans = alloc_and_load_sharable_switch_trans(num_switch,
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trans_sram_bit, R_minW_nmos, R_minW_pmos);
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for (from_node = 0; from_node < num_rr_nodes; from_node++) {
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from_rr_type = rr_node[from_node].type;
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switch (from_rr_type) {
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case CHANX:
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case CHANY:
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num_edges = rr_node[from_node].num_edges;
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for (iedge = 0; iedge < num_edges; iedge++) {
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to_node = rr_node[from_node].edges[iedge];
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to_rr_type = rr_node[to_node].type;
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switch (to_rr_type) {
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case CHANX:
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case CHANY:
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iswitch = rr_node[from_node].switches[iedge];
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if (switch_inf[iswitch].buffered) {
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iseg = seg_index_of_sblock(from_node, to_node);
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shared_buffer_trans[iseg] = std::max(
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shared_buffer_trans[iseg],
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sharable_switch_trans[iswitch]);
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ntrans_no_sharing += unsharable_switch_trans[iswitch]
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+ sharable_switch_trans[iswitch];
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ntrans_sharing += unsharable_switch_trans[iswitch];
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} else if (from_node < to_node) {
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/* Pass transistor shared by two edges -- only count once. *
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* Also, no part of a pass transistor is sharable. */
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ntrans_no_sharing += unsharable_switch_trans[iswitch];
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ntrans_sharing += unsharable_switch_trans[iswitch];
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}
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break;
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case IPIN:
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num_inputs_to_cblock[to_node]++;
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max_inputs_to_cblock = std::max(max_inputs_to_cblock,
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num_inputs_to_cblock[to_node]);
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iseg = seg_index_of_cblock(from_rr_type, to_node);
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/* Xifan TANG: cb switches*/
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if (OPEN == switches_to_cblock[to_node]) {
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switches_to_cblock[to_node] = rr_node[from_node].switches[iedge];
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} else {
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assert(switches_to_cblock[to_node] == rr_node[from_node].switches[iedge]);
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}
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/* END */
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if (cblock_counted[iseg] == FALSE) {
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cblock_counted[iseg] = TRUE;
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ntrans_sharing += trans_track_to_cblock_buf;
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ntrans_no_sharing += trans_track_to_cblock_buf;
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}
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n");
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vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n",
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from_node, from_rr_type, to_node, to_rr_type);
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exit(1);
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break;
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} /* End switch on to_rr_type. */
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} /* End for each edge. */
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/* Now add in the shared buffer transistors, and reset some flags. */
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if (from_rr_type == CHANX) {
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for (i = rr_node[from_node].xlow - 1;
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i <= rr_node[from_node].xhigh; i++) {
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ntrans_sharing += shared_buffer_trans[i];
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shared_buffer_trans[i] = 0.;
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}
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for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh;
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i++)
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cblock_counted[i] = FALSE;
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} else { /* CHANY */
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for (j = rr_node[from_node].ylow - 1;
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j <= rr_node[from_node].yhigh; j++) {
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ntrans_sharing += shared_buffer_trans[j];
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shared_buffer_trans[j] = 0.;
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}
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for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh;
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j++)
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cblock_counted[j] = FALSE;
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}
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break;
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case OPIN:
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num_edges = rr_node[from_node].num_edges;
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shared_opin_buffer_trans = 0.;
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for (iedge = 0; iedge < num_edges; iedge++) {
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iswitch = rr_node[from_node].switches[iedge];
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ntrans_no_sharing += unsharable_switch_trans[iswitch]
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+ sharable_switch_trans[iswitch];
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ntrans_sharing += unsharable_switch_trans[iswitch];
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shared_opin_buffer_trans = std::max(shared_opin_buffer_trans,
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sharable_switch_trans[iswitch]);
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}
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ntrans_sharing += shared_opin_buffer_trans;
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break;
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default:
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break;
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} /* End switch on from_rr_type */
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} /* End for all nodes */
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free(cblock_counted);
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free(shared_buffer_trans);
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free(unsharable_switch_trans);
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free(sharable_switch_trans);
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/* Now add in the input connection block transistors. */
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input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG:*/switches_to_cblock,
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max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit);
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free(num_inputs_to_cblock);
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/* Xifan TANG: cb switches */
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free(switches_to_cblock);
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/* END */
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ntrans_sharing += input_cblock_trans;
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ntrans_no_sharing += input_cblock_trans;
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vpr_printf(TIO_MESSAGE_INFO, "\n");
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vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n");
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vpr_printf(TIO_MESSAGE_INFO, "\tAssuming no buffer sharing (pessimistic). Total: %#g, per logic tile: %#g\n",
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ntrans_no_sharing, ntrans_no_sharing / (float) (nx * ny));
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vpr_printf(TIO_MESSAGE_INFO, "\tAssuming buffer sharing (slightly optimistic). Total: %#g, per logic tile: %#g\n",
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ntrans_sharing, ntrans_sharing / (float) (nx * ny));
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vpr_printf(TIO_MESSAGE_INFO, "\n");
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}
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void count_unidir_routing_transistors(t_segment_inf * segment_inf,
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float R_minW_nmos, float R_minW_pmos, float sram_area) {
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boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */
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int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */
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/* Xifan TANG: cb switches*/
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int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */
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/* END */
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/* corresponding to IPINs will be 0. */
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t_rr_type from_rr_type, to_rr_type;
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int i, j, iseg, from_node, to_node, iedge, num_edges, maxlen;
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int max_inputs_to_cblock, cost_index, seg_type, switch_type;
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float input_cblock_trans;
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const float trans_sram_bit = sram_area;
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/* Two variables below are the accumulator variables that add up all the *
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* transistors in the routing. Make doubles so that they don't stop *
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* incrementing once adding a switch makes a change of less than 1 part in *
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* 10^7 to the total. If this still isn't good enough (adding 1 part in *
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* 10^15 will still be thrown away), compute the transistor count in *
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* "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing *
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* the partial sums together. */
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double ntrans;
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/* Buffers from the routing to the ipin cblock inputs, and from the ipin *
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* cblock outputs to the logic block, respectively. Assume minimum size n *
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* transistors, and ptransistors sized to make the pull-up R = pull-down R. */
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float trans_track_to_cblock_buf;
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float trans_cblock_to_lblock_buf;
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max_inputs_to_cblock = 0;
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/* Assume the two buffers below are 4x minimum drive strength (enough to *
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* drive a fanout of up to 16 pretty nicely -- should cover a reasonable *
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* wiring C plus the fanout. */
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trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos,
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R_minW_pmos);
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trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos,
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R_minW_pmos);
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num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int));
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/* Xifan TANG: cb switches*/
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switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int));
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for (i = 0; i < num_rr_nodes; i++) {
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switches_to_cblock[i] = OPEN;
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}
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/* END */
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maxlen = std::max(nx, ny) + 1;
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cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean));
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ntrans = 0;
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for (from_node = 0; from_node < num_rr_nodes; from_node++) {
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from_rr_type = rr_node[from_node].type;
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switch (from_rr_type) {
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case CHANX:
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case CHANY:
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num_edges = rr_node[from_node].num_edges;
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cost_index = rr_node[from_node].cost_index;
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seg_type = rr_indexed_data[cost_index].seg_index;
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/* Xifan TANG: Switch Segment Pattern Support
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* we should consider the switch no in the segment but in the rr_node
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*/
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if (rr_node[from_node].unbuf_switched) {
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switch_type = rr_node[from_node].driver_switch;
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} else {
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switch_type = segment_inf[seg_type].wire_switch;
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assert(
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segment_inf[seg_type].wire_switch == segment_inf[seg_type].opin_switch);
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}
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assert(switch_inf[switch_type].mux_trans_size >= 1);
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/* can't be smaller than min sized transistor */
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assert(rr_node[from_node].num_opin_drivers == 0);
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/* undir has no opin or wire switches */
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assert(rr_node[from_node].num_wire_drivers == 0);
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/* undir has no opin or wire switches */
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/* Each wire segment begins with a multipexer followed by a driver for unidirectional */
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/* Each multiplexer contains all the fan-in to that routing node */
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/* Add up area of multiplexer */
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ntrans += trans_per_mux(rr_node[from_node].fan_in, trans_sram_bit,
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switch_inf[switch_type].mux_trans_size, switch_inf[switch_type]);
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/* Add up area of buffer */
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/* Xifan TANG: Switch Segment Pattern Support*/
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if ((switch_inf[switch_type].buf_size == 0)&&(0 != strcmp("unbuf_mux",switch_inf[switch_type].type))) {
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ntrans += trans_per_buf(switch_inf[switch_type].R, R_minW_nmos,
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R_minW_pmos);
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} else {
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ntrans += switch_inf[switch_type].buf_size;
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}
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for (iedge = 0; iedge < num_edges; iedge++) {
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to_node = rr_node[from_node].edges[iedge];
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to_rr_type = rr_node[to_node].type;
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switch (to_rr_type) {
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case CHANX:
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case CHANY:
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break;
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case IPIN:
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num_inputs_to_cblock[to_node]++;
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max_inputs_to_cblock = std::max(max_inputs_to_cblock,
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num_inputs_to_cblock[to_node]);
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iseg = seg_index_of_cblock(from_rr_type, to_node);
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/* Xifan TANG: cb switches*/
|
|
if (OPEN == switches_to_cblock[to_node]) {
|
|
switches_to_cblock[to_node] = rr_node[from_node].switches[iedge];
|
|
} else {
|
|
assert(switches_to_cblock[to_node] == rr_node[from_node].switches[iedge]);
|
|
}
|
|
/* END */
|
|
|
|
if (cblock_counted[iseg] == FALSE) {
|
|
cblock_counted[iseg] = TRUE;
|
|
ntrans += trans_track_to_cblock_buf;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n");
|
|
vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n",
|
|
from_node, from_rr_type, to_node, to_rr_type);
|
|
exit(1);
|
|
break;
|
|
|
|
} /* End switch on to_rr_type. */
|
|
|
|
} /* End for each edge. */
|
|
|
|
/* Reset some flags */
|
|
if (from_rr_type == CHANX) {
|
|
for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh;
|
|
i++)
|
|
cblock_counted[i] = FALSE;
|
|
|
|
} else { /* CHANY */
|
|
for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh;
|
|
j++)
|
|
cblock_counted[j] = FALSE;
|
|
|
|
}
|
|
break;
|
|
case OPIN:
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
|
|
} /* End switch on from_rr_type */
|
|
} /* End for all nodes */
|
|
|
|
/* Now add in the input connection block transistors. */
|
|
|
|
input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG*/switches_to_cblock,
|
|
max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit);
|
|
|
|
free(cblock_counted);
|
|
free(num_inputs_to_cblock);
|
|
|
|
/* Xifan TANG: cb switches */
|
|
free(switches_to_cblock);
|
|
/* END */
|
|
|
|
ntrans += input_cblock_trans;
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO, "\n");
|
|
vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n");
|
|
vpr_printf(TIO_MESSAGE_INFO, "\tTotal routing area: %#g, per logic tile: %#g\n", ntrans, ntrans / (float) (nx * ny));
|
|
}
|
|
|
|
static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock,
|
|
int max_inputs_to_cblock, float trans_cblock_to_lblock_buf,
|
|
float trans_sram_bit) {
|
|
|
|
/* Computes the transistors in the input connection block multiplexers and *
|
|
* the buffers from connection block outputs to the logic block input pins. *
|
|
* For speed, I precompute the number of transistors in the multiplexers of *
|
|
* interest. */
|
|
|
|
float *trans_per_cblock; /* [0..max_inputs_to_cblock] */
|
|
float trans_count;
|
|
int i, num_inputs;
|
|
|
|
trans_per_cblock = (float *) my_malloc(
|
|
(max_inputs_to_cblock + 1) * sizeof(float));
|
|
|
|
trans_per_cblock[0] = 0.; /* i.e., not an IPIN or no inputs */
|
|
|
|
/* With one or more inputs, add the mux and output buffer. I add the output *
|
|
* buffer even when the number of inputs = 1 (i.e. no mux) because I assume *
|
|
* I need the drivability just for metal capacitance. */
|
|
/*
|
|
for (i = 1; i <= max_inputs_to_cblock; i++)
|
|
trans_per_cblock[i] = trans_per_mux(i, trans_sram_bit,
|
|
ipin_mux_trans_size) + trans_cblock_to_lblock_buf;
|
|
*/
|
|
|
|
trans_count = 0.;
|
|
|
|
for (i = 0; i < num_rr_nodes; i++) {
|
|
num_inputs = num_inputs_to_cblock[i];
|
|
/* Xifan TANG: consider cblock structure in area estimation */
|
|
assert((0 < num_inputs)||(0 == num_inputs));
|
|
if (0 < num_inputs) {
|
|
assert(OPEN != switches_to_cblock[i]);
|
|
trans_count += trans_per_mux(num_inputs, trans_sram_bit,
|
|
ipin_mux_trans_size, switch_inf[switches_to_cblock[i]]) + trans_cblock_to_lblock_buf;
|
|
}
|
|
/* END */
|
|
/* trans_count += trans_per_cblock[num_inputs]; */
|
|
}
|
|
|
|
free(trans_per_cblock);
|
|
return (trans_count);
|
|
}
|
|
|
|
static float *
|
|
alloc_and_load_unsharable_switch_trans(int num_switch, float trans_sram_bit,
|
|
float R_minW_nmos) {
|
|
|
|
/* Loads up an array that says how many transistors are needed to implement *
|
|
* the unsharable portion of each switch type. The SRAM bit of a switch and *
|
|
* the pass transistor (forming either the entire switch or the output part *
|
|
* of a tri-state buffer) are both unsharable. */
|
|
|
|
float *unsharable_switch_trans, Rpass;
|
|
int i;
|
|
|
|
unsharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float));
|
|
|
|
for (i = 0; i < num_switch; i++) {
|
|
|
|
if (switch_inf[i].buffered == FALSE) {
|
|
Rpass = switch_inf[i].R;
|
|
} else { /* Buffer. Set Rpass = Rbuf = 1/2 Rtotal. */
|
|
Rpass = switch_inf[i].R / 2.;
|
|
}
|
|
|
|
unsharable_switch_trans[i] = trans_per_R(Rpass, R_minW_nmos)
|
|
+ trans_sram_bit;
|
|
}
|
|
|
|
return (unsharable_switch_trans);
|
|
}
|
|
|
|
static float *
|
|
alloc_and_load_sharable_switch_trans(int num_switch, float trans_sram_bit,
|
|
float R_minW_nmos, float R_minW_pmos) {
|
|
|
|
/* Loads up an array that says how many transistor are needed to implement *
|
|
* the sharable portion of each switch type. The SRAM bit of a switch and *
|
|
* the pass transistor (forming either the entire switch or the output part *
|
|
* of a tri-state buffer) are both unsharable. Only the buffer part of a *
|
|
* buffer switch is sharable. */
|
|
|
|
float *sharable_switch_trans, Rbuf;
|
|
int i;
|
|
|
|
sharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float));
|
|
|
|
for (i = 0; i < num_switch; i++) {
|
|
|
|
if (switch_inf[i].buffered == FALSE) {
|
|
sharable_switch_trans[i] = 0.;
|
|
} else { /* Buffer. Set Rbuf = Rpass = 1/2 Rtotal. */
|
|
Rbuf = switch_inf[i].R / 2.;
|
|
sharable_switch_trans[i] = trans_per_buf(Rbuf, R_minW_nmos,
|
|
R_minW_pmos);
|
|
}
|
|
}
|
|
|
|
return (sharable_switch_trans);
|
|
}
|
|
|
|
/*mrFPGA: Xifan TANG, make this function accessible out of this source file*/
|
|
//static
|
|
/*end */
|
|
float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) {
|
|
|
|
/* Returns the number of minimum width transistor area equivalents needed to *
|
|
* implement this buffer. Assumes a stage ratio of 4, and equal strength *
|
|
* pull-up and pull-down paths. */
|
|
|
|
int num_stage, istage;
|
|
float trans_count, stage_ratio, Rstage;
|
|
|
|
if (Rbuf > 0.6 * R_minW_nmos || Rbuf <= 0.) { /* Use a single-stage buffer */
|
|
trans_count = trans_per_R(Rbuf, R_minW_nmos)
|
|
+ trans_per_R(Rbuf, R_minW_pmos);
|
|
} else { /* Use a multi-stage buffer */
|
|
|
|
/* Target stage ratio = 4. 1 minimum width buffer, then num_stage bigger *
|
|
* ones. */
|
|
|
|
num_stage = nint(log10(R_minW_nmos / Rbuf) / log10(4.));
|
|
num_stage = std::max(num_stage, 1);
|
|
stage_ratio = pow((float)(R_minW_nmos / Rbuf), (float)( 1. / (float) num_stage));
|
|
|
|
Rstage = R_minW_nmos;
|
|
trans_count = 0.;
|
|
|
|
for (istage = 0; istage <= num_stage; istage++) {
|
|
trans_count += trans_per_R(Rstage, R_minW_nmos)
|
|
+ trans_per_R(Rstage, R_minW_pmos);
|
|
Rstage /= stage_ratio;
|
|
}
|
|
}
|
|
|
|
return (trans_count);
|
|
}
|
|
|
|
static float trans_per_mux(int num_inputs, float trans_sram_bit,
|
|
float pass_trans_area, t_switch_inf target_switch) {
|
|
|
|
/* Returns the number of transistors needed to build a pass transistor mux. *
|
|
* DOES NOT include input buffers or any output buffer. *
|
|
* Attempts to select smart multiplexer size depending on number of inputs *
|
|
* For multiplexers with inputs 4 or less, one level is used, more has two *
|
|
* levels. */
|
|
float ntrans, sram_trans, pass_trans;
|
|
int num_second_stage_trans;
|
|
int mux_basis = 0;
|
|
|
|
/* Xifan TANG: Original VPR area function is below, I replace them by considering more physical design parameters */
|
|
/*
|
|
if (num_inputs <= 1) {
|
|
return (0);
|
|
} else if (num_inputs == 2) {
|
|
pass_trans = 2 * pass_trans_area;
|
|
sram_trans = 1 * trans_sram_bit;
|
|
} else if (num_inputs <= 4) {
|
|
*/
|
|
/* One-hot encoding */
|
|
/*
|
|
pass_trans = num_inputs * pass_trans_area;
|
|
sram_trans = num_inputs * trans_sram_bit;
|
|
} else {
|
|
*/
|
|
/* This is a large multiplexer so design it using a two-level multiplexer *
|
|
* + 0.00001 is to make sure exact square roots two don't get rounded down *
|
|
* to one lower level. */
|
|
/*
|
|
num_second_stage_trans = (int)floor((float)sqrt((float)num_inputs) + 0.00001);
|
|
pass_trans = (num_inputs + num_second_stage_trans) * pass_trans_area;
|
|
sram_trans = (ceil(
|
|
(float) num_inputs / num_second_stage_trans - 0.00001)
|
|
+ num_second_stage_trans) * trans_sram_bit;
|
|
if (num_second_stage_trans == 2) {
|
|
*/
|
|
/* Can use one-bit instead of a two-bit one-hot encoding for the second stage */
|
|
/* Eliminates one sram bit counted earlier */
|
|
/*
|
|
sram_trans -= 1 * trans_sram_bit;
|
|
}
|
|
}
|
|
*/
|
|
/* Xifan TANG: new function starts */
|
|
if (num_inputs <= 1) {
|
|
return 0;
|
|
}
|
|
/* Consider different structure */
|
|
switch (target_switch.structure) {
|
|
case SPICE_MODEL_STRUCTURE_TREE:
|
|
sram_trans = trans_sram_bit * determine_tree_mux_level(num_inputs);
|
|
pass_trans = (num_inputs - 1)* 2 * pass_trans_area;
|
|
break;
|
|
case SPICE_MODEL_STRUCTURE_ONELEVEL:
|
|
sram_trans = trans_sram_bit * num_inputs;
|
|
pass_trans = (num_inputs * pass_trans_area);
|
|
break;
|
|
case SPICE_MODEL_STRUCTURE_MULTILEVEL:
|
|
assert(1 < target_switch.switch_num_level);
|
|
mux_basis = determine_num_input_basis_multilevel_mux(num_inputs, target_switch.switch_num_level);
|
|
sram_trans = trans_sram_bit * target_switch.switch_num_level * mux_basis;
|
|
num_second_stage_trans = (int)pow((double)mux_basis, (double)(target_switch.switch_num_level - 1));
|
|
pass_trans = ((num_second_stage_trans - 1) * mux_basis/(mux_basis-1)) * pass_trans_area
|
|
+ num_inputs * pass_trans_area;
|
|
break;
|
|
default:
|
|
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid structure for switch(name=%s)!\n",
|
|
__FILE__, __LINE__, target_switch.name);
|
|
exit(1);
|
|
}
|
|
|
|
ntrans = pass_trans + sram_trans;
|
|
return (ntrans);
|
|
}
|
|
|
|
static float trans_per_R(float Rtrans, float R_minW_trans) {
|
|
|
|
/* Returns the number of minimum width transistor area equivalents needed *
|
|
* to make a transistor with Rtrans, given that the resistance of a minimum *
|
|
* width transistor of this type is R_minW_trans. */
|
|
|
|
float trans_area;
|
|
|
|
if (Rtrans <= 0.) /* Assume resistances are nonsense -- use min. width */
|
|
return (1.);
|
|
|
|
if (Rtrans >= R_minW_trans)
|
|
return (1.);
|
|
|
|
/* Area = minimum width area (1) + 0.5 for each additional unit of width. *
|
|
* The 50% factor takes into account the "overlapping" that occurs in *
|
|
* horizontally-paralleled transistors, and the need for only one spacing, *
|
|
* not two (i.e. two min W transistors need two spaces; a 2W transistor *
|
|
* needs only 1). */
|
|
|
|
trans_area = 0.5 * R_minW_trans / Rtrans + 0.5;
|
|
return (trans_area);
|
|
}
|