194 lines
6.4 KiB
C
194 lines
6.4 KiB
C
/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "rr_graph_swseg.h"
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#include "vpr_utils.h"
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#include "route_common.h"
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/* Include spice support headers*/
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#include "linkedlist.h"
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#include "fpga_x2p_types.h"
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#include "fpga_x2p_globals.h"
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#include "spice_globals.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_pbtypes_utils.h"
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#include "fpga_x2p_bitstream_utils.h"
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#include "spice_utils.h"
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#include "spice_pbtypes.h"
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#include "spice_primitive.h"
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void fprint_pb_primitive_generic(FILE* fp,
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char* subckt_prefix,
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t_phy_pb* prim_phy_pb,
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t_pb_type* prim_pb_type,
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int index,
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t_spice_model* spice_model) {
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int num_sram_port = 0;
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t_spice_model_port** sram_port = NULL;
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int i;
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int num_sram = 0;
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int expected_num_sram = 0;
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int* sram_bits = NULL;
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int cur_num_sram = 0;
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int mapped_logical_block_index = OPEN;
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char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
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char* port_prefix = NULL;
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char* sram_vdd_port_name = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Asserts */
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assert((SPICE_MODEL_FF == spice_model->type)
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||(SPICE_MODEL_HARDLOGIC == spice_model->type)
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||(SPICE_MODEL_IOPAD == spice_model->type));
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/* Find mapped logical block */
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if (NULL != prim_phy_pb) {
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for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) {
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mapped_logical_block_index = prim_phy_pb->logical_block[i];
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/* Back-annotate to logical block */
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logical_block[mapped_logical_block_index].mapped_spice_model = spice_model;
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logical_block[mapped_logical_block_index].mapped_spice_model_index = spice_model->cnt;
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fprintf(fp, "***** Logical block mapped to this primitive node: %s *****\n",
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logical_block[mapped_logical_block_index].name);
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}
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}
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/* Generate Subckt for pb_type*/
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/*
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index);
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*/
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/* Simplify the port prefix, make SPICE netlist readable */
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index);
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/* Decode SRAM bits */
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num_sram = count_num_sram_bits_one_spice_model(spice_model, -1);
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sram_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
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/* what is the SRAM bit of a mode? */
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/* If logical block is not NULL, we need to decode the sram bit */
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if ( 0 < num_sram_port) {
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assert (1 == num_sram_port);
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if (NULL != prim_phy_pb) {
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sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram);
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} else { /* get default mode_bits */
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sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram);
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}
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assert(expected_num_sram == num_sram);
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}
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/* Get current counter of mem_bits, bl and wl */
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cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info);
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/* Definition line */
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fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix);
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/* print ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
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/* Local vdd and gnd*/
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fprintf(fp, "svdd sgnd\n");
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/* Definition ends*/
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/* Call the iopad subckt*/
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fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt);
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/* Only dump the global ports belonging to a spice_model
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* Do not go recursive, we can freely define global ports anywhere in SPICE netlist
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*/
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if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) {
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fprintf(fp, "+ ");
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}
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/* print regular ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
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/* Print inout port */
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if (SPICE_MODEL_IOPAD == spice_model->type) {
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fprintf(fp, " %s%s[%d] ",
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gio_inout_prefix,
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spice_model->prefix,
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spice_model->cnt);
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}
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/* Print SRAM ports */
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for (i = 0; i < num_sram; i++) {
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fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]);
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/* We need the invertered signal for better convergency */
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fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, 1 - sram_bits[i]);
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}
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/* Local vdd and gnd, spice_model name,
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* TODO: Global vdd for i/o pad to split?
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*/
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fprintf(fp, "%s_%s[%d] sgnd %s\n",
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spice_tb_global_vdd_port_name,
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spice_model->prefix,
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spice_model->cnt,
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spice_model->name);
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/* Print the encoding in SPICE netlist for debugging */
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fprintf(fp, "***** SRAM bits for %s[%d] *****\n",
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spice_model->prefix,
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spice_model->cnt);
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fprintf(fp, "*****");
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for (i = 0; i < num_sram; i++) {
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fprintf(fp, "%d", sram_bits[i]);
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}
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fprintf(fp, "*****\n");
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/* Call SRAM subckts*/
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/* Give the VDD port name for SRAMs */
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sram_vdd_port_name = (char*)my_malloc(sizeof(char)*
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(strlen(spice_tb_global_vdd_io_sram_port_name)
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+ 1 ));
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sprintf(sram_vdd_port_name, "%s",
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spice_tb_global_vdd_io_sram_port_name);
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/* Now Print SRAMs one by one */
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for (i = 0; i < num_sram; i++) {
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fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name);
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}
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/* Store the configuraion bit to linked-list */
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add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram,
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num_sram, sram_bits);
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/* End */
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fprintf(fp, ".eom\n");
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/* Update the spice_model counter */
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spice_model->cnt++;
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/*Free*/
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my_free(formatted_subckt_prefix);
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my_free(port_prefix);
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my_free(sram_vdd_port_name);
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my_free(sram_port);
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return;
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}
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