674 lines
26 KiB
C
674 lines
26 KiB
C
/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "rr_graph_swseg.h"
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#include "vpr_utils.h"
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#include "route_common.h"
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/* Include spice support headers*/
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#include "linkedlist.h"
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#include "fpga_x2p_types.h"
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#include "fpga_x2p_globals.h"
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#include "spice_globals.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_pbtypes_utils.h"
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#include "fpga_x2p_lut_utils.h"
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#include "fpga_x2p_bitstream_utils.h"
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#include "spice_utils.h"
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#include "spice_mux.h"
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#include "spice_pbtypes.h"
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#include "spice_lut.h"
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/***** Subroutines *****/
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void fprint_spice_lut_subckt(FILE* fp,
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t_spice_model* spice_model) {
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int num_input_port = 0;
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t_spice_model_port** input_port = NULL;
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int num_output_port = 0;
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t_spice_model_port** output_port = NULL;
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int num_sram_port = 0;
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t_spice_model_port** sram_port = NULL;
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int iport, ipin;
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int sram_port_index = OPEN;
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int mode_port_index = OPEN;
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int mode_lsb = 0;
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int num_dumped_port = 0;
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char* mode_inport_postfix = "_mode";
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int jport, jpin, pin_cnt;
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int modegate_num_input_port = 0;
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int modegate_num_input_pins = 0;
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int modegate_num_output_port = 0;
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t_spice_model_port** modegate_input_port = NULL;
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t_spice_model_port** modegate_output_port = NULL;
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char* required_gate_type = NULL;
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enum e_spice_model_gate_type required_gate_model_type;
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float total_width;
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int width_cnt;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
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__FILE__, __LINE__);
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}
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/* Find input ports, output ports and sram ports*/
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input_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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sram_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
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/* Check */
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if (FALSE == spice_model->design_tech_info.lut_info->frac_lut) {
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/* when fracturable LUT is considered
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* More than 1 output is allowed
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* Only two SRAM ports are allowed
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*/
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assert(1 == num_input_port);
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assert(1 == num_output_port);
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assert(1 == num_sram_port);
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} else {
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assert (TRUE == spice_model->design_tech_info.lut_info->frac_lut);
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/* when fracturable LUT is considered
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* More than 1 output is allowed
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* Only two SRAM ports are allowed
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*/
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assert(1 == num_input_port);
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for (iport = 0; iport < num_output_port; iport++) {
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assert(0 < output_port[iport]->size);
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}
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assert(2 == num_sram_port);
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}
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fprintf(fp, "***** Auto-generated LUT info: spice_model_name = %s, size = %d *****\n",
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spice_model->name, input_port[0]->size);
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/* Define the subckt*/
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fprintf(fp, ".subckt %s ", spice_model->name); /* Subckt name*/
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/* Input ports*/
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for (iport = 0; iport < num_input_port; iport++) {
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for (ipin = 0; ipin < input_port[iport]->size; ipin++) {
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fprintf(fp, "%s%d ", input_port[iport]->prefix, ipin);
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}
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}
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/* output ports*/
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for (iport = 0; iport < num_output_port; iport++) {
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for (ipin = 0; ipin < output_port[iport]->size; ipin++) {
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fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin);
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}
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}
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/* sram ports */
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/* Print configuration ports*/
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num_dumped_port = 0;
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for (iport = 0; iport < num_sram_port; iport++) {
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/* By pass mode select ports */
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if (TRUE == sram_port[iport]->mode_select) {
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continue;
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}
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assert(FALSE == sram_port[iport]->mode_select);
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for (ipin = 0; ipin < sram_port[iport]->size; ipin++) {
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fprintf(fp, "%s%d ", sram_port[iport]->prefix, ipin);
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}
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sram_port_index = iport;
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num_dumped_port++;
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}
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/* Print mode configuration ports*/
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num_dumped_port = 0;
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for (iport = 0; iport < num_sram_port; iport++) {
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/* By pass mode select ports */
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if (FALSE == sram_port[iport]->mode_select) {
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continue;
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}
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assert(TRUE == sram_port[iport]->mode_select);
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for (ipin = 0; ipin < sram_port[iport]->size; ipin++) {
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fprintf(fp, "%s_out%d ", sram_port[iport]->prefix, ipin);
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}
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mode_port_index = iport;
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num_dumped_port++;
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}
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/* Check if all required SRAMs ports*/
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if (TRUE == spice_model->design_tech_info.lut_info->frac_lut) {
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if (1 != num_dumped_port) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d]) Fracturable LUT (spice_model_name=%s) must have 1 mode port!\n",
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__FILE__, __LINE__, spice_model->name);
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exit(1);
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}
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}
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/* local vdd and gnd*/
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fprintf(fp, "svdd sgnd\n");
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/* Input buffers */
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assert (1 == num_input_port);
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assert (NULL != input_port);
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/* If this is a regular LUT, we give a default tri_state_map */
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if (FALSE == spice_model->design_tech_info.lut_info->frac_lut) {
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for (iport = 0; iport < num_input_port; iport++) {
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if (NULL == input_port[iport]->tri_state_map) {
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input_port[iport]->tri_state_map = (char*)my_calloc(input_port[iport]->size, sizeof(char));
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} else {
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vpr_printf(TIO_MESSAGE_WARNING,
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"(File:%s, [LINE%d])Overwrite the tri-state map for the LUT inputs (name=%s)!\n",
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__FILE__, __LINE__, spice_model->name);
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}
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for (ipin = 0; ipin < input_port[iport]->size; ipin++) {
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input_port[iport]->tri_state_map[ipin] = '-';
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}
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}
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}
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/* Add AND/OR gates if this is a fracturable LUT */
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for (iport = 0; iport < num_input_port; iport++) {
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/* Initialize lsb */
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mode_lsb = 0;
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for (ipin = 0; ipin < input_port[iport]->size; ipin++) {
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if ('0' == input_port[iport]->tri_state_map[ipin]) {
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required_gate_type = "AND";
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required_gate_model_type = SPICE_MODEL_GATE_AND;
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}
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if ('1' == input_port[iport]->tri_state_map[ipin]) {
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required_gate_type = "OR";
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required_gate_model_type = SPICE_MODEL_GATE_OR;
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}
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/* First check if we have the required gates*/
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switch (input_port[iport]->tri_state_map[ipin]) {
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case '-':
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break;
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case '0':
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case '1':
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/* Check: we must have an AND2/OR2 gate */
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if (NULL == input_port[iport]->spice_model) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) is not defined!\n",
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__FILE__, __LINE__, required_gate_type,
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input_port[iport]->prefix, spice_model->name);
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exit(1);
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}
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if ((SPICE_MODEL_GATE != input_port[iport]->spice_model->type)
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|| (required_gate_model_type != input_port[iport]->spice_model->design_tech_info.gate_info->type)) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) is not defined as a AND logic gate!\n",
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__FILE__, __LINE__, required_gate_type,
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input_port[iport]->prefix, spice_model->name);
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exit(1);
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}
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/* Check input ports */
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modegate_input_port = find_spice_model_ports(input_port[iport]->spice_model, SPICE_MODEL_PORT_INPUT, &modegate_num_input_port, TRUE);
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modegate_num_input_pins = 0;
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for (jport = 0; jport < modegate_num_input_port; jport++) {
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modegate_num_input_pins += modegate_input_port[jport]->size;
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}
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if (2 != modegate_num_input_pins) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) should have only 2 input pins!\n",
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__FILE__, __LINE__, required_gate_type,
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input_port[iport]->prefix, spice_model->name);
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exit(1);
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}
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/* Check output ports */
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modegate_output_port = find_spice_model_ports(input_port[iport]->spice_model, SPICE_MODEL_PORT_OUTPUT, &modegate_num_output_port, TRUE);
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if ( (1 != modegate_num_output_port)
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|| (1 != modegate_output_port[0]->size)) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) should have only 1 output!\n",
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__FILE__, __LINE__, required_gate_type,
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input_port[iport]->prefix, spice_model->name);
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exit(1);
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}
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/* Instance the AND2/OR2 gate */
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fprintf(fp, "X%s_%s%d ",
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input_port[iport]->spice_model->prefix,
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input_port[iport]->prefix, ipin);
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pin_cnt = 0;
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for (jport = 0; jport < modegate_num_input_port; jport++) {
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for (jpin = 0; jpin < modegate_input_port[jport]->size; jpin++) {
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if (0 == pin_cnt) {
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fprintf(fp, "%s%d",
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input_port[iport]->prefix, ipin);
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} else if (1 == pin_cnt) {
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fprintf(fp, " %s_out%d",
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sram_port[mode_port_index]->prefix, mode_lsb);
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}
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pin_cnt++;
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}
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}
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assert(2 == pin_cnt);
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fprintf(fp, " %s%s%d",
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input_port[0]->prefix, mode_inport_postfix, ipin);
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mode_lsb++;
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/* local vdd and gnd*/
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fprintf(fp, " svdd sgnd");
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/* Call subckt name */
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fprintf(fp, " %s\n", input_port[iport]->spice_model->name);
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/* Free ports */
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my_free(modegate_input_port);
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my_free(modegate_output_port);
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(file:%s,line[%d]) invalid LUT tri_state_map = %s ",
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__FILE__, __LINE__, input_port[iport]->tri_state_map);
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exit(1);
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}
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}
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/* Check if we have dumped all the SRAM ports for mode selection */
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if ((OPEN != mode_port_index)
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&&(mode_lsb != sram_port[mode_port_index]->size)) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d]) SPICE model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n",
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__FILE__, __LINE__,
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spice_model->name, input_port[iport]->tri_state_map[ipin], input_port[iport]->size);
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exit(1);
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}
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/* Create inverters between input port and its inversion */
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for (ipin = 0; ipin < input_port[iport]->size; ipin++) {
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switch (input_port[iport]->tri_state_map[ipin]) {
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case '-':
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/* For negative input of LUT MUX*/
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/* Output inverter with maximum size allowed
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* until the rest of width is smaller than threshold */
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total_width = spice_model->lut_input_buffer->size * spice_model->lut_input_buffer->f_per_stage;
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width_cnt = 0;
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while (total_width > max_width_per_trans) {
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fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'",
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ipin, width_cnt,
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input_port[iport]->prefix, ipin,
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ipin, max_width_per_trans);
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fprintf(fp, "\n");
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/* Update */
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total_width = total_width - max_width_per_trans;
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width_cnt++;
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}
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/* Print if we still have to */
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if (total_width > 0) {
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fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'",
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ipin, width_cnt,
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input_port[iport]->prefix, ipin,
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ipin, total_width);
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fprintf(fp, "\n");
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}
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/* For postive input of LUT MUX, we use the tapered_buffer subckt directly */
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assert(1 == spice_model->lut_input_buffer->tapered_buf);
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fprintf(fp, "X%s_in%d %s%d lut_mux_in%d svdd sgnd tapbuf_level%d_f%d\n",
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spice_model->lut_input_buffer->spice_model->prefix, ipin,
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input_port[iport]->prefix, ipin, ipin,
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spice_model->lut_input_buffer->tap_buf_level,
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spice_model->lut_input_buffer->f_per_stage);
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fprintf(fp, "\n");
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break;
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case '0':
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case '1':
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/* For negative input of LUT MUX*/
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/* Output inverter with maximum size allowed
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* until the rest of width is smaller than threshold */
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total_width = spice_model->lut_input_buffer->size * spice_model->lut_input_buffer->f_per_stage;
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width_cnt = 0;
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while (total_width > max_width_per_trans) {
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fprintf(fp, "Xinv0_in%d_no%d %s%s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'",
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ipin, width_cnt,
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input_port[iport]->prefix, mode_inport_postfix, ipin,
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ipin, max_width_per_trans);
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fprintf(fp, "\n");
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/* Update */
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total_width = total_width - max_width_per_trans;
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width_cnt++;
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}
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/* Print if we still have to */
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if (total_width > 0) {
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fprintf(fp, "Xinv0_in%d_no%d %s%s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'",
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ipin, width_cnt,
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input_port[iport]->prefix, mode_inport_postfix, ipin,
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ipin, total_width);
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fprintf(fp, "\n");
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}
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/* For postive input of LUT MUX, we use the tapered_buffer subckt directly */
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assert(1 == spice_model->lut_input_buffer->tapered_buf);
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fprintf(fp, "X%s_in%d %s%s%d lut_mux_in%d svdd sgnd tapbuf_level%d_f%d\n",
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spice_model->lut_input_buffer->spice_model->prefix, ipin,
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input_port[iport]->prefix, mode_inport_postfix, ipin, ipin,
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spice_model->lut_input_buffer->tap_buf_level,
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spice_model->lut_input_buffer->f_per_stage);
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fprintf(fp, "\n");
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(file:%s,line[%d]) invalid LUT tri_state_map = %s ",
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__FILE__, __LINE__, input_port[iport]->tri_state_map);
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exit(1);
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}
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}
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}
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/* Output buffers already included in LUT MUX */
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/* LUT MUX*/
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assert(sram_port[sram_port_index]->size == (int)pow(2.,(double)(input_port[0]->size)));
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fprintf(fp, "Xlut_mux ");
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/* SRAM ports of LUT, they are inputs of lut_muxes*/
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for (ipin = 0; ipin < sram_port[sram_port_index]->size; ipin++) {
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assert(FALSE == sram_port[sram_port_index]->mode_select);
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fprintf(fp, "%s%d ", sram_port[sram_port_index]->prefix, ipin);
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}
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/* Output port, LUT output is LUT MUX output*/
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for (iport = 0; iport < num_output_port; iport++) {
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for (ipin = 0; ipin < output_port[iport]->size; ipin++) {
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fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin);
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}
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}
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/* Connect MUX configuration port to LUT inputs */
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/* input port, LUT input is LUT MUX sram*/
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for (iport = 0; iport < num_input_port; iport++) {
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for (ipin = 0; ipin < input_port[iport]->size; ipin++) {
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fprintf(fp, "lut_mux_in%d lut_mux_in%d_inv ", ipin, ipin);
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}
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}
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/* Local vdd and gnd*/
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fprintf(fp, "svdd sgnd %s_mux_size%d\n",
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spice_model->name, sram_port[sram_port_index]->size);
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/* End of LUT subckt*/
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fprintf(fp, ".eom\n");
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/* Free */
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my_free(input_port);
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my_free(output_port);
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my_free(sram_port);
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return;
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}
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/* Print LUT subckts into a SPICE file*/
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void generate_spice_luts(char* subckt_dir,
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int num_spice_model,
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t_spice_model* spice_models) {
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FILE* fp = NULL;
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char* sp_name = my_strcat(subckt_dir, luts_spice_file_name);
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int imodel = 0;
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/* Create FILE*/
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fp = fopen(sp_name, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name);
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exit(1);
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}
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fprint_spice_head(fp,"LUTs");
|
|
|
|
for (imodel = 0; imodel < num_spice_model; imodel++) {
|
|
if ((SPICE_MODEL_LUT == spice_models[imodel].type)
|
|
&&(NULL == spice_models[imodel].model_netlist)) {
|
|
fprint_spice_lut_subckt(fp, &(spice_models[imodel]));
|
|
}
|
|
}
|
|
|
|
/* Close*/
|
|
fclose(fp);
|
|
|
|
return;
|
|
}
|
|
|
|
void fprint_pb_primitive_lut(FILE* fp,
|
|
char* subckt_prefix,
|
|
t_phy_pb* prim_phy_pb,
|
|
t_pb_type* prim_pb_type,
|
|
int index,
|
|
t_spice_model* spice_model) {
|
|
int i, j;
|
|
int* lut_sram_bits = NULL; /* decoded SRAM bits */
|
|
int* mode_sram_bits = NULL; /* decoded SRAM bits */
|
|
int* sram_bits = NULL; /* decoded SRAM bits */
|
|
int* truth_table_length = 0;
|
|
char*** truth_table = NULL;
|
|
|
|
int lut_size = 0;
|
|
int num_input_port = 0;
|
|
t_spice_model_port** input_ports = NULL;
|
|
int num_output_port = 0;
|
|
t_spice_model_port** output_ports = NULL;
|
|
int num_sram_port = 0;
|
|
t_spice_model_port** sram_ports = NULL;
|
|
t_spice_model_port* lut_sram_port = NULL;
|
|
t_spice_model_port* mode_bit_port = NULL;
|
|
int num_lut_pin_nets;
|
|
int* lut_pin_net = NULL;
|
|
int mapped_logical_block_index;
|
|
|
|
char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
|
|
t_pb_type* cur_pb_type = prim_pb_type;
|
|
char* port_prefix = NULL;
|
|
|
|
int cur_num_sram = 0;
|
|
int num_sram = 0;
|
|
int num_lut_sram = 0;
|
|
int num_mode_sram = 0;
|
|
int expected_num_sram = 0;
|
|
char* sram_vdd_port_name = NULL;
|
|
|
|
/* Ensure a valid file handler*/
|
|
if (NULL == fp) {
|
|
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
|
|
__FILE__, __LINE__);
|
|
exit(1);
|
|
}
|
|
|
|
/* Asserts */
|
|
assert(SPICE_MODEL_LUT == spice_model->type);
|
|
|
|
/* Determine size of LUT*/
|
|
input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
|
|
output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
|
|
sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
|
|
assert(1 == num_input_port);
|
|
lut_size = input_ports[0]->size;
|
|
num_sram = (int)pow(2.,(double)(lut_size));
|
|
/* Find SRAM ports for truth tables and mode bits */
|
|
sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
|
|
assert((1 == num_sram_port) || (2 == num_sram_port));
|
|
for (i = 0; i < num_sram_port; i++) {
|
|
if (FALSE == sram_ports[i]->mode_select) {
|
|
lut_sram_port = sram_ports[i];
|
|
num_lut_sram = sram_ports[i]->size;
|
|
assert (num_lut_sram == (int)pow(2.,(double)(lut_size)));
|
|
} else {
|
|
assert (TRUE == sram_ports[i]->mode_select);
|
|
mode_bit_port = sram_ports[i];
|
|
num_mode_sram = sram_ports[i]->size;
|
|
}
|
|
}
|
|
/* Must have a lut_sram_port, while mode_bit_port is optional */
|
|
assert (NULL != lut_sram_port);
|
|
|
|
/* Count the number of configuration bits */
|
|
num_sram = count_num_sram_bits_one_spice_model(spice_model, -1);
|
|
|
|
/* Get current counter of mem_bits, bl and wl */
|
|
cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info);
|
|
|
|
/* If this is an idle LUT, we give an empty truth table */
|
|
if ((NULL == prim_phy_pb)
|
|
|| ((NULL != prim_phy_pb && (0 == prim_phy_pb->num_logical_blocks)))) {
|
|
lut_sram_bits = (int*) my_calloc ( num_lut_sram, sizeof(int));
|
|
for (i = 0; i < num_lut_sram; i++) {
|
|
lut_sram_bits[i] = lut_sram_port->default_val;
|
|
}
|
|
} else {
|
|
assert (NULL != prim_phy_pb);
|
|
/* Allocate truth tables */
|
|
truth_table_length = (int*) my_malloc (sizeof(int) * prim_phy_pb->num_logical_blocks);
|
|
truth_table = (char***) my_malloc (sizeof(char**) * prim_phy_pb->num_logical_blocks);
|
|
|
|
/* Output log for debugging purpose */
|
|
fprintf(fp, "***** Logic Block %s *****\n",
|
|
prim_phy_pb->spice_name_tag);
|
|
|
|
/* Find truth tables and decode them one by one
|
|
* Fracturable LUT may have multiple truth tables,
|
|
* which should be grouped in a unique one
|
|
*/
|
|
for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) {
|
|
mapped_logical_block_index = prim_phy_pb->logical_block[i];
|
|
/* For wired LUT we provide a default truth table */
|
|
if (TRUE == prim_phy_pb->is_wired_lut[i]) {
|
|
/* TODO: assign post-routing lut truth table!!!*/
|
|
get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net);
|
|
truth_table[i] = assign_post_routing_wired_lut_truth_table(prim_phy_pb->rr_graph->rr_node[prim_phy_pb->lut_output_pb_graph_pin[i]->rr_node_index_physical_pb].vpack_net_num,
|
|
num_lut_pin_nets, lut_pin_net, &truth_table_length[i]);
|
|
} else {
|
|
assert (FALSE == prim_phy_pb->is_wired_lut[i]);
|
|
assert (VPACK_COMB == logical_block[mapped_logical_block_index].type);
|
|
/* Get the mapped vpack_net_num of this physical LUT pb */
|
|
get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net);
|
|
/* consider LUT pin remapping when assign lut truth tables */
|
|
/* Match truth table and post-routing results */
|
|
truth_table[i] = assign_post_routing_lut_truth_table(&logical_block[mapped_logical_block_index],
|
|
num_lut_pin_nets, lut_pin_net, &truth_table_length[i]);
|
|
}
|
|
/* Adapt truth table for a fracturable LUT
|
|
* TODO: Determine fixed input bits for this truth table:
|
|
* 1. input bits within frac_level (all '-' if not specified)
|
|
* 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1')
|
|
*/
|
|
adapt_truth_table_for_frac_lut(prim_phy_pb->lut_output_pb_graph_pin[i],
|
|
truth_table_length[i], truth_table[i]);
|
|
/* Output log for debugging purpose */
|
|
if (WIRED_LUT_LOGICAL_BLOCK_ID == mapped_logical_block_index) {
|
|
fprintf(fp, "***** Wired LUT: mapped to a buffer *****\n");
|
|
} else {
|
|
fprintf(fp, "***** Mapped Logic Block[%d] %s *****\n",
|
|
i, logical_block[mapped_logical_block_index].name);
|
|
}
|
|
fprintf(fp, "***** Net map *****\n*");
|
|
for (j = 0; j < num_lut_pin_nets; j++) {
|
|
if (OPEN == lut_pin_net[j]) {
|
|
fprintf(fp, " OPEN, ");
|
|
} else {
|
|
assert (OPEN != lut_pin_net[j]);
|
|
fprintf(fp, " %s, ", vpack_net[lut_pin_net[j]].name);
|
|
}
|
|
}
|
|
fprintf(fp, "\n");
|
|
fprintf(fp, "***** Truth Table *****\n");
|
|
for (j = 0; j < truth_table_length[i]; j++) {
|
|
fprintf(fp, "*%s\n", truth_table[i][j]);
|
|
}
|
|
}
|
|
/* Generate base sram bits*/
|
|
lut_sram_bits = generate_frac_lut_sram_bits(prim_phy_pb, truth_table_length, truth_table, lut_sram_port->default_val);
|
|
}
|
|
|
|
/* Add mode bits */
|
|
if (NULL != mode_bit_port) {
|
|
if (NULL != prim_phy_pb) {
|
|
mode_sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram);
|
|
} else { /* get default mode_bits */
|
|
mode_sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram);
|
|
}
|
|
assert(expected_num_sram == num_mode_sram);
|
|
}
|
|
|
|
/* Merge the SRAM bits from LUT SRAMs and Mode selection */
|
|
assert ( num_sram == num_lut_sram + num_mode_sram );
|
|
sram_bits = (int*)my_calloc(num_sram, sizeof(int));
|
|
/* LUT SRAMs go first and then mode bits */
|
|
memcpy(sram_bits, lut_sram_bits, num_lut_sram * sizeof(int));
|
|
if (NULL != mode_bit_port) {
|
|
memcpy(sram_bits + num_lut_sram, mode_sram_bits, num_mode_sram * sizeof(int));
|
|
}
|
|
|
|
/* Subckt definition*/
|
|
fprintf(fp, ".subckt %s%s[%d] ", formatted_subckt_prefix, cur_pb_type->name, index);
|
|
/* Print inputs, outputs, inouts, clocks, NO SRAMs*/
|
|
/*
|
|
port_prefix = (char*)my_malloc(sizeof(char)*
|
|
(strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 +
|
|
strlen(my_itoa(index)) + 1 + 1));
|
|
sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, cur_pb_type->name, index);
|
|
*/
|
|
/* Simplify the prefix, make the SPICE netlist readable*/
|
|
port_prefix = (char*)my_malloc(sizeof(char)*
|
|
(strlen(cur_pb_type->name) + 1 +
|
|
strlen(my_itoa(index)) + 1 + 1));
|
|
sprintf(port_prefix, "%s[%d]", cur_pb_type->name, index);
|
|
|
|
/* Only dump the global ports belonging to a spice_model
|
|
* Do not go recursive, we can freely define global ports anywhere in SPICE netlist
|
|
*/
|
|
rec_fprint_spice_model_global_ports(fp, spice_model, FALSE);
|
|
|
|
fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type);
|
|
/* SRAM bits are fixed in this subckt, no need to define them here*/
|
|
/* Local Vdd and gnd*/
|
|
fprintf(fp, "svdd sgnd\n");
|
|
/* Definition ends*/
|
|
|
|
/* Call SRAM subckts*/
|
|
/* Give the VDD port name for SRAMs */
|
|
sram_vdd_port_name = (char*)my_malloc(sizeof(char)*
|
|
(strlen(spice_tb_global_vdd_lut_sram_port_name)
|
|
+ 1 ));
|
|
sprintf(sram_vdd_port_name, "%s",
|
|
spice_tb_global_vdd_lut_sram_port_name);
|
|
/* Now Print SRAMs one by one */
|
|
for (i = 0; i < num_sram; i++) {
|
|
fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name);
|
|
}
|
|
|
|
/* Call LUT subckt*/
|
|
fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt);
|
|
/* Connect inputs*/
|
|
/* Connect outputs*/
|
|
fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type);
|
|
/* Connect srams*/
|
|
for (i = 0; i < num_sram; i++) {
|
|
assert( (0 == sram_bits[i]) || (1 == sram_bits[i]) );
|
|
fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]);
|
|
}
|
|
|
|
/* vdd should be connected to special global wire gvdd_lut and gnd,
|
|
* Every LUT has a special VDD for statistics
|
|
*/
|
|
fprintf(fp, "gvdd_%s[%d] sgnd %s\n", spice_model->prefix, spice_model->cnt, spice_model->name);
|
|
/* TODO: Add a nodeset for convergence */
|
|
|
|
/* End of subckt*/
|
|
fprintf(fp, ".eom\n");
|
|
|
|
/* Store the configuraion bit to linked-list */
|
|
add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram,
|
|
num_sram, sram_bits);
|
|
|
|
spice_model->cnt++;
|
|
|
|
/*Free*/
|
|
my_free(formatted_subckt_prefix);
|
|
my_free(input_ports);
|
|
my_free(output_ports);
|
|
my_free(sram_ports);
|
|
my_free(sram_bits);
|
|
my_free(port_prefix);
|
|
my_free(sram_vdd_port_name);
|
|
|
|
return;
|
|
}
|