144 lines
5.4 KiB
C++
144 lines
5.4 KiB
C++
/********************************************************************
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* This file includes functions that output bitstream database
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* to files in different formats
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*******************************************************************/
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#include <chrono>
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#include <ctime>
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#include <fstream>
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#include "vtr_assert.h"
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#include "util.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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#include "bitstream_manager_utils.h"
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#include "bitstream_writer.h"
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/********************************************************************
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* This function write header information to a bitstream file
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*******************************************************************/
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static
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void write_bitstream_xml_file_head(std::fstream& fp) {
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check_file_handler(fp);
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auto end = std::chrono::system_clock::now();
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std::time_t end_time = std::chrono::system_clock::to_time_t(end);
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fp << "<!--" << std::endl;
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fp << "\t- Architecture independent bitstream" << std::endl;
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fp << "\t- Author: Xifan TANG" << std::endl;
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fp << "\t- Organization: University of Utah" << std::endl;
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fp << "\t- Date: " << std::ctime(&end_time) ;
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fp << "-->" << std::endl;
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fp << std::endl;
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}
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/********************************************************************
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* Recursively write the bitstream of a block to a xml file
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* This function will use a Depth-First Search in outputting bitstream
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* for each block
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* 1. For block with bits as children, we will output the XML lines
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* 2. For block without bits/child blocks, we can return
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* 3. For block with child blocks, we visit each child recursively
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*******************************************************************/
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static
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void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
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const BitstreamManager& bitstream_manager,
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const ConfigBlockId& block) {
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check_file_handler(fp);
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/* Dive to child blocks if this block has any */
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for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) {
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rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block);
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}
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if (0 == bitstream_manager.block_bits(block).size()) {
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return;
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}
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/* Write the bits of this block */
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fp << "<bitstream_block index=\"" << size_t(block) << "\">" << std::endl;
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std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, block);
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/* Output hierarchy of this parent*/
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fp << "\t<hierarchy>" << std::endl;
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size_t hierarchy_counter = 0;
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for (const ConfigBlockId& temp_block : block_hierarchy) {
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fp << "\t\t<instance level=\"" << hierarchy_counter << "\"";
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fp << " name=\"" << bitstream_manager.block_name(temp_block) << "\"";
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fp << "/>" << std::endl;
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hierarchy_counter++;
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}
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fp << "\t</hierarchy>" << std::endl;
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/* Output child bits under this block */
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size_t bit_counter = 0;
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fp << "\t<bitstream>" << std::endl;
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for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) {
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fp << "\t\t<bit";
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fp << " memory_port=\"" << generate_configuration_chain_data_out_name() << "[" << bit_counter << "]" << "\"";
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fp << " value=\"" << bitstream_manager.bit_value(child_bit) << "\"";
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fp << "/>" << std::endl;
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bit_counter++;
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}
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fp << "\t</bitstream>" << std::endl;
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fp << "</bitstream_block>" <<std::endl;
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}
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/********************************************************************
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* Write the bitstream to a file without binding to the configuration
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* procotols of a given FPGA fabric in XML format
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*
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* Notes:
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* This is a very generic representation for bitstream that are implemented
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* by VPR engine. It shows the bitstream for each blocks in the FPGA
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* architecture that users are modeling.
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* This function can be used to:
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* 1. Debug the bitstream decoding to see if there is any bug
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* 2. Create an intermediate file to reorganize a bitstream for
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* specific FPGAs
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* 3. TODO: support FASM format
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*******************************************************************/
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void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
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const std::string& fname) {
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing %lu architecture independent bitstream into XML file (%s)...\n",
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bitstream_manager.bits().size(), fname.c_str());
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/* Start time count */
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clock_t t_start = clock();
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/* Create the file stream */
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std::fstream fp;
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fp.open(fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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/* Put down a brief introduction */
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write_bitstream_xml_file_head(fp);
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std::string top_block_name = generate_fpga_top_module_name();
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/* Find the top block, which has not parents */
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std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
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/* Make sure we have only 1 top block and its name matches the top module */
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VTR_ASSERT(1 == top_block.size());
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VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0])));
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/* Write bitstream, block by block, in a recursive way */
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rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0]);
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/* Close file handler */
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fp.close();
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/* End time count */
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clock_t t_end = clock();
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float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing bitstream to file took %g seconds...\n",
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run_time_sec);
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}
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