597 lines
21 KiB
ReStructuredText
597 lines
21 KiB
ReStructuredText
.. _openfpga_setup_commands:
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Setup OpenFPGA
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--------------
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read_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Read the XML file about architecture description (see details in :ref:`arch_generality`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file openfpga_arch.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_arch
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~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML architecture file to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file arch_echo.xml``
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.. option:: --verbose
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Show verbose log
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read_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_simulation_setting.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML simulation settings to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``.
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See details about file format at :ref:`simulation_setting`.
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.. option:: --verbose
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Show verbose log
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read_openfpga_bitstream_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about bitstream settings (see details in :ref:`file_formats_bitstream_setting`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file bitstream_setting.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_bitstream_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML bitstream settings to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_bitstream_setting_echo.xml``.
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See details about file format at :ref:`file_formats_bitstream_setting`.
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.. option:: --verbose
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Show verbose log
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.. _openfpga_setup_command_read_openfpga_clock_arch:
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read_openfpga_clock_arch
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~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about programmable clock network (see details in :ref:`file_formats_clock_network`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file clock_network.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_clock_arch
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~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA programmable clock network to an XML file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file clock_network_echo.xml``.
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See details about file format at :ref:`file_formats_clock_network`.
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.. option:: --verbose
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Show verbose log
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append_clock_rr_graph
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~~~~~~~~~~~~~~~~~~~~~
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Build the routing resource graph based on an defined programmable clock network, and append it to the existing routing resource graph built by VPR.
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Use command :ref:`openfpga_setup_command_read_openfpga_clock_arch`` to load the clock network.
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.. option:: --verbose
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Show verbose log
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route_clock_rr_graph
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~~~~~~~~~~~~~~~~~~~~
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Route clock signals on the built routing resource graph which contains a programmable clock network.
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Clock signals will be auto-detected and routed based on pin constraints which are provided by users.
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.. option:: --pin_constraints_file <string> or -pcf <string>
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Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml``. Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`.
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.. note:: If there is a global net, e.g., ``clk`` or ``reset``, which will be driven by an internal resource, it should also be defined in the PCF file.
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.. option:: --disable_unused_trees
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Disable entire clock trees when they are not used by any clock nets. Useful to reduce clock power
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.. option:: --disable_unused_spines
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Disable part of the clock tree which are used by clock nets. Useful to reduce clock power
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.. option:: --verbose
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Show verbose log
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link_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Annotate the OpenFPGA architecture to VPR data base
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.. option:: --activity_file <string>
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Specify the signal activity file. For example, ``--activity_file counter.act``.
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This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at :ref:`simulation_setting`.
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.. option:: --sort_gsb_chan_node_in_edges
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Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
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.. option:: --verbose
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Show verbose log
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write_gsb_to_xml
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~~~~~~~~~~~~~~~~
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Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
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.. option:: --file <string> or -f <string>
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Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
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For example, ``--file /temp/gsb_output``
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.. option:: --unique
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Only output unique GSBs to XML files
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.. option:: --exclude_rr_info
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Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.
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.. option:: --exclude <string>
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Exclude part of the GSB data to be outputted. Can be [``sb``|``cbx``|``cby``]. Users can exclude multiple parts by using a splitter ``,``.
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For example,
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- ``--exclude sb``
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- ``--exclude sb,cbx``
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.. option:: --gsb_names <string>
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Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ``,``.
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When specified, only the GSBs whose names match the list will be outputted to files.
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If not specified, all the GSBs will be outputted.
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.. note:: When option ``--unique`` is enable, the given name of GSBs should match the unique modules!
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For example,
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- ``--gsb_names gsb_2__4_,gsb_3__2_``
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- ``--gsb_names gsb_2__4_``
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.. option:: --verbose
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Show verbose log
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.. note:: This command is used to help users to study the difference between GSBs
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check_netlist_naming_conflict
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Check and correct any naming conflicts in the BLIF netlist
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This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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.. option:: --fix
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Apply fix-up to the names that violate the syntax
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.. option:: --report <string>
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Report the naming fix-up to an XML-based log file. For example, ``--report rename.xml``
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pb_pin_fixup
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~~~~~~~~~~~~
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Apply fix-up to clustering nets based on routing results
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.. note:: Suggest to skip the similar fix-up applied by VPR through options ``--skip_sync_clustering_and_routing_results on`` when calling vpr in openfpga shell.
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.. warning:: This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for *Look-Up Tables* (LUTs) but you want to enable logic equivalent for input pins of LUTs
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.. warning:: This command may be deprecated in future
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.. option:: --map_global_net_to_msb
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If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice. For example, when ``--clock_modeling ideal`` is selected when running VPR, global nets will not be routed and their pin mapping on programmable blocks may be revoked by other nets due to optimization. Therefore, this command will restore the pin mapping for the global nets and pick a spare pin on programmable blocks. This option is to set a preference when mapping the global nets to spare pins.
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.. option:: --verbose
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Show verbose log
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lut_truth_table_fixup
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~~~~~~~~~~~~~~~~~~~~~
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Apply fix-up to Look-Up Table truth tables based on packing results
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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.. option:: --verbose
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Show verbose log
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.. _cmd_build_fabric:
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build_fabric
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~~~~~~~~~~~~
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Build the module graph.
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.. option:: --compress_routing
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Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
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.. option:: --group_tile <string>
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Group fine-grained programmable blocks, connection blocks and switch blocks into tiles. Once enabled, tiles will be added to the top-level module. Otherwise, the top-level module consists of programmable blocks, connection blocks and switch blocks. The tile style can be customized through a file. See details in :ref:`file_formats_tile_config_file`. When enabled, the Verilog netlists will contain additional netlists that model tiles (see details in :ref:`fabric_netlists_tiles`).
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.. warning:: This option does not support ``--duplicate_grid_pin``!
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.. warning:: This option requires ``--compress_routing`` to be enabled!
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.. option:: --group_config_block
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Group configuration memory blocks under each CLB/SB/CB etc. into a centralized configuration memory blocks, as depicted in :numref:`fig_group_config_block_overview`. When disabled, the configuration memory blocks are placed in a distributed way under CLB/SB/CB etc. For example, each programming resource, e.g., LUT, has a dedicated configuration memory block, being placed in the same module. When enabled, as illustrated in :numref:`fig_group_config_block_hierarchy`, the physical memory block locates under a CLB, driving a number of logical memory blocks which are close to the programmable resources. The logical memory blocks contain only pass-through wires which can be optimized out during physical design phase.
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.. _fig_group_config_block_overview:
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.. figure:: ./figures/group_config_block_overview.png
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:width: 100%
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Impact on grouping configuable blocks: before and after
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.. _fig_group_config_block_hierarchy:
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.. figure:: ./figures/group_config_block_hierarchy.png
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:width: 100%
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Netlist hierarchy on grouped configuable blocks
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.. option:: --name_module_using_index
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Use index in module names, e.g., ``cbx_2_``. This is applied to routing modules, as well as tile modules when option ``--group_tile`` is enabled. If disabled, the module name consist of coordinates, e.g., ``cbx_1__2_``.
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.. option:: --duplicate_grid_pin
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Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
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.. option:: --load_fabric_key <string>
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Load an external fabric key from an XML file. For example, ``--load_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
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.. option:: --generate_random_fabric_key
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Generate a fabric key in a random way
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.. option:: --write_fabric_key <string>.
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Output current fabric key to an XML file. For example, ``--write_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
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.. warning:: This option will be deprecated. Use :ref:`cmd_write_fabric_key` as a replacement.
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.. option:: --frame_view
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Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
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.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
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.. option:: --verbose
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Show verbose log
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.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
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.. _cmd_write_fabric_key:
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write_fabric_key
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~~~~~~~~~~~~~~~~
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Output current fabric key to an XML file. For example, ``write_fabric_key --file fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
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.. note:: This command can output module-level keys while the ``--write_fabric_key`` option in command ``build_fabric`` does NOT support! Strongly recommend to use this command to obtain fabric key.
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file fabric_key_echo.xml``.
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.. option:: --include_module_keys
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Output module-level keys to the file.
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.. option:: --verbose
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Show verbose log
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.. _cmd_add_fpga_core_to_fabric:
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add_fpga_core_to_fabric
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~~~~~~~~~~~~~~~~~~~~~~~
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Add a wrapper module ``fpga_core`` as an intermediate layer to FPGA fabric. After this command, the existing module ``fpga_top`` will remain the top-level module while there is a new module ``fpga_core`` under it. Under fpga_core, there will be the detailed building blocks.
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.. option:: --io_naming <string>
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This is optional. Specify the I/O naming rules when connecting I/Os of ``fpga_core`` module to the top-level module ``fpga_top``. If not defined, the ``fpga_top`` will be the same as ``fpga_core`` w.r.t. ports. See details about the file format of I/O naming rules in :ref:`file_formats_io_naming_file`.
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.. option:: --instance_name <string>
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This is optional. Specify the instance name to be used when instanciate the ``fpga_core`` module under the top-level module ``fpga_top``. If not defined, by default it is ``fpga_core_inst``.
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.. option:: --frame_view
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Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
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.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
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.. option:: --verbose
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Show verbose log
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.. _openfpga_setup_commands_write_fabric_hierarchy:
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write_fabric_hierarchy
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~~~~~~~~~~~~~~~~~~~~~~
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Write the hierarchy of FPGA fabric graph to a YAML file
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.. option:: --file <string> or -f <string>
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Specify the file name to write the hierarchy. See details in :ref:`file_format_fabric_hierarchy_file`.
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.. option:: --depth <int>
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Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
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.. option:: --module <regexp>
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Specify the root module name(s) which should be considered. By default, it is ``fpga_top``. Note that regular expression is supported. For example, ``grid_*`` will output all the modules with a prefix of ``grid_``
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.. option:: --filter <regexp>
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Specify the filter which allows user to select modules to appear under each root module tree. By default, it is ``*``. Regular expression is supported. For example, ``*mux*`` will output all the modules which contains ``mux``. In the other words, the filter defines a white list.
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.. option:: --exclude_empty_modules
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Exclude modules with no qualified children (match the names defined through filter) from the output file
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.. option:: --verbose
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Show verbose log
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.. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
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.. _openfpga_setup_commands_write_fabric_io_info:
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write_fabric_io_info
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~~~~~~~~~~~~~~~~~~~~
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Write the I/O information of FPGA fabric to an XML file
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.. option:: --file <string> or -f <string>
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Specify the file name to write the I/O information
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.. option:: --no_time_stamp
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Do not print time stamp in output files
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.. option:: --verbose
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Show verbose log
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.. note:: This file is designed for pin constraint file conversion.
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.. _openfpga_setup_commands_pcf2place:
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pcf2place
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~~~~~~~~~
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Convert a Pin Constraint File (.pcf, see details in :ref:`file_format_pcf_file`) to a `placement file <https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#placement-file-format-place>`_)
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.. option:: --pcf <string>
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Specify the path to the users' pin constraint file
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.. option:: --blif <string>
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Specify the path to the users' post-synthesis netlist
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.. option:: --fpga_io_map <string>
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Specify the path to the FPGA I/O location. Achieved by the command :ref:`openfpga_setup_commands_write_fabric_io_info`
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.. option:: --pin_table <string>
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Specify the path to the pin table file, which describes the pin mapping between chip I/Os and FPGA I/Os. See details in :ref:`file_format_pin_table_file`
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.. option:: --fpga_fix_pins <string>
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Specify the path to the placement file which will be outputted by running this command
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.. option:: --pin_table_direction_convention <string>
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Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``.
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.. option:: --no_time_stamp
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Do not print time stamp in output files
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.. option:: --reduce_error_to_warning
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Reduce error to warning while reading commands in pcf file
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.. warning:: Exercise extreme caution when adding this option – be sure you completely understand why the issue is being flagged, and why it is OK to treat as a warning instead of an error.
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.. option:: --verbose
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Show verbose log
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.. _openfpga_setup_commands_rename_modules:
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rename_modules
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~~~~~~~~~~~~~~
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Rename modules of an FPGA fabric with a given set of naming rules
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.. option:: --file <string>
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Specify the file path which contain the naming rules. See details in :ref:`file_formats_module_naming_file`.
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.. option:: --verbose
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Show verbose log
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.. _openfpga_setup_commands_write_module_naming_rules:
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write_module_naming_rules
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~~~~~~~~~~~~~~~~~~~~~~~~~
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Output the naming rules for each module of an FPGA fabric to a given file
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.. option:: --file <string>
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Specify the file path to be written to
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.. option:: --no_time_stamp
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Do not print time stamp in output files
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.. option:: --verbose
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Show verbose log
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.. _openfpga_setup_commands_write_fabric_pin_physical_location:
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write_fabric_pin_physical_location
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Output the physical location of each pin for each module of an FPGA fabric to a given file
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.. option:: --file <string>
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|
||
Specify the file path to be written to. See details in :ref:`file_format_fabric_pin_physical_location_file`.
|
||
|
||
.. option:: --module <string>
|
||
|
||
Specify the name of modules to be considered. Support regular expression, e.g., ``tile*``. When provided, only pins of selected modules will be outputted. By default, a wildcard ``*`` is considered, which means all the modules will be considered.
|
||
|
||
.. option:: --show_invalid_side
|
||
|
||
Show sides for each pin, even these pin does not have a specific valid side. This is mainly used for debugging.
|
||
|
||
.. option:: --no_time_stamp
|
||
|
||
Do not print time stamp in output files
|
||
|
||
.. option:: --verbose
|
||
|
||
Show verbose log
|
||
|
||
.. _openfpga_setup_commands_report_reference:
|
||
|
||
report_reference
|
||
~~~~~~~~~~~~~~~~~~~~
|
||
|
||
Write reference information of each child module under a given parent module to a YAML file
|
||
|
||
.. option:: --file <string> or -f <string>
|
||
|
||
Specify the file name to write the reference information. See details in :ref:`file_format_reference_file`.
|
||
|
||
.. option:: --module <string>
|
||
|
||
Specify the parent module name, under which the references of each child module will be reported.
|
||
|
||
.. option:: --no_time_stamp
|
||
|
||
Do not print time stamp in output files
|
||
|
||
.. option:: --verbose
|
||
|
||
Show verbose info
|
||
|
||
|
||
.. _openfpga_setup_commands_read_unique_blocks:
|
||
|
||
read_unique_blocks
|
||
~~~~~~~~~~~~~~~~~~~~
|
||
|
||
Read information of unique blocks from a given file.
|
||
|
||
.. option:: --file <string>
|
||
|
||
Specify the file which contains unique block information. See details in :ref:`file_formats_unique_blocks`.
|
||
|
||
.. option:: --type <string>
|
||
|
||
Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML.
|
||
|
||
.. option:: --verbose
|
||
|
||
Show verbose info
|
||
|
||
.. _openfpga_setup_commands_write_unique_blocks:
|
||
|
||
write_unique_blocks
|
||
~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
Write information of unique blocks from internal data structure to a given file.
|
||
|
||
.. option:: --file <string>
|
||
|
||
Specify the file which we will write unique block information to. See details in :ref:`file_formats_unique_blocks`.
|
||
|
||
.. option:: --type <string>
|
||
|
||
Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML.
|
||
|
||
.. option:: --verbose
|
||
|
||
Show verbose info
|
||
|