225 lines
6.3 KiB
ReStructuredText
225 lines
6.3 KiB
ReStructuredText
.. _developer_naming_convention:
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Naming Convention
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=================
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.. _developer_naming_convention_cell_names:
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Cell Names
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----------
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.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_ff_model_names`!
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.. note:: we refer to standard cell wrapper here. Wrappers are built to make netlists portable between PDKs as well as across standard cell libraries in a PDK.
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For code readability, the cell name should follow the convention
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<Cell_Function><Set_Features><Reset_Features><Output_Features><Drive_Strength>_<Wrapper>
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.. option:: Cell_Function
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Name of logic function, e.g., AND2, XNOR3, etc.
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.. option:: Set_Features
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This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a set signal, its existence and polarity must be inferreable by the cell name. The available options are
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- S: Asynchronous active-high set
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- SYNS: Synchronous active-hight set
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- SN: Asynchronous active-low set
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- SYNSN: Synchronous active-low set
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.. note:: For cells without set, this keyword should be empty
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.. option:: Reset_Features
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This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a reset signal, its existence and polarity must be inferreable by the cell name. The available options are
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- R: Asynchronous active-high reset
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- SYNR: Synchronous active-hight reset
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- RN: Asynchronous active-low reset
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- SYNRN: Synchronous active-low reset
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.. note:: For cells without reset, this keyword should be empty
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.. option:: Output_Features
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This is mainly for sequential cells, e.g., D-type flip-flops.
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- If not specified, the sequential cell contains a pair of differential outputs, e.g., ``Q`` and ``QN``
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- If specified, the sequential cell only contains single output, e.g., ``Q``
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The available options are
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- Q: single output which is positive
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- QN: single ouput which is negative
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.. note:: For cells without reset, this keyword should be empty
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.. option:: Drive_Strength
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This is to specify the drive strength of a cell
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- If not specified, we assume minimum drive strength, i.e., ``D0``.
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- If specified, we expect a format of ``D<int>``, where the integer indicates the drive strength
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.. option:: Wrapper
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This is to specify if the cell is a wrapper of an existing standard cell
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- If not specified, we assume this cell contains RTL
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- If specified, we assume this cell is a wrapper of an existing standard cell
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A quick example
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NAND2D4_WRAPPER
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represents a wrapper for a standard cell that is a 2-input NAND gate with a drive strength of 4
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Another example
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SDFFSSYNRNQ
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represents a scan-chain flip-flop which contains
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- Asynchronous active-high set
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- Synchronous active-low reset
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- Single output
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Pin Names
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---------
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.. note:: Please use lowercase as much as you can
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For code readability, the pin name should follow the convention
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<Pin_Name>_<Polarity><Direction>
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.. option:: Pin_Name
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Represents the pin name
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.. option:: Polarity
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Represents polarity of the pin, it can be
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- ``n`` denotes a negative-enable (active_low) signal
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.. note:: When not specified, by default we assume this is a postive-enable (active-high) signal
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.. option:: Direction
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Represents the direction of a pin, it can be
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- ``i`` denotes an input signal
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- ``o`` denotes an output signal
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A quick example
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clk_ni
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represents an input clock signal which is negative-enable
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Another example
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q_no
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represents an output Q signal which is negative to the input
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.. _developer_naming_convention_ff_model_names:
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Flip-flop Model Names
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---------------------
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.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`!
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.. note:: we refer to virtual cell model (used by VPR and Yosys for cell mapping) here.
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For code readability, D-type flip-flop model names should follow the convention
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<Sync_Type>dff<Trigger_Type><Set_Type><Reset_Type>
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.. option:: Sync_Features
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Represents if the reset/set is synchronous or asynchronous to the clock, it can be
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- ``s`` denotes a synchronous behavior
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- an empty string "" denotes an asynchronous behavior, e.g., ``ffr``
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.. option:: Trigger_Type
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Represents if the flip-flop is triggered by rising edge or falling edge of a clock, it can be
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- ``n`` means triggered by failling edge
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- an empty string "" means triggered by rising edge, e.g., ``ff``
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.. option:: Set_Type
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Represents if the flip-flop has a set and the polarity of the set, it can be
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- ``s`` means that the flip-flop has an active-high set pin
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- ``sn`` means that the flip-flop has an active-low set pin
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- an empty string "" means the flip-flop does not have a set pin, e.g., ``ff``
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.. option:: Reset_Type
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Represents if the flip-flop has a reset and the polarity of the reset, it can be
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- ``r`` means that the flip-flop has an active-high reset pin
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- ``rn`` means that the flip-flop has an active-low reset pin
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- an empty string "" means the flip-flop does not have a reset pin, e.g., ``ff``
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A quick example
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ffnrn
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represents a flip-flop
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- triggered by falling edge
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- with an asynchronous active-low reset
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Another example
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sffs
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represents a flip-flop
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- triggered by rising edge
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- with a synchronous active-high set
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.. _developer_naming_convention_mux_model_names:
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Multiplexer Model Names
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-----------------------
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.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`!
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.. note:: Here, we refer to the circuit model name used in OpenFPGA architecture file.
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For code readability, a routing multiplexer circuit model name should follow the convention
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<Location>_mux_<Load>
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.. option:: Location
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Represents the location of the routing multiplexers, it can be
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- ``cb`` denotes a routing multiplexer in a connection block
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- ``sb`` denotes a routing multiplexer in a switch block
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- ``pb`` denotes a routing multiplexer in a programmable block
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.. option:: Load
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Represents the output load condition of the routing multiplexers, it can be
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- ``highload`` means that the routing multiplexer has to drive a very high capacitive load, which potentially requires a big buffer at output
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- an empty string "" means the routing multiplexer requires only a typical buffer size.
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A quick example
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pb_mux_highload
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represents a routing multiplexer used in a programmable block which drives a high capacitive load
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