57 lines
1.4 KiB
Verilog
Executable File
57 lines
1.4 KiB
Verilog
Executable File
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, clk, reset);
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input[31:0] Xinport;
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input[31:0] Yinport;
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input[31:0] Uinport;
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input[31:0] Aport;
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input[31:0] DXport;
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input clk;
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input reset;
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output[31:0] Xoutport;
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output[31:0] Youtport;
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output[31:0] Uoutport;
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reg[31:0] Xoutport;
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reg[31:0] Youtport;
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reg[31:0] Uoutport;
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reg[31:0] x_var;
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reg[31:0] y_var;
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reg[31:0] u_var;
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wire[31:0] temp;
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reg looping;
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assign temp = u_var * DXport;
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always @(posedge clk)
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begin
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if (reset == 1'b1)
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begin
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looping <= 1'b0;
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x_var <= 0;
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y_var <= 0;
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u_var <= 0;
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end
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else
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if (looping == 1'b0)
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begin
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x_var <= Xinport;
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y_var <= Yinport;
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u_var <= Uinport;
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looping <= 1'b1;
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end
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else if (x_var < Aport)
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begin
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u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
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y_var <= y_var + temp;//(u_var * DXport);
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x_var <= x_var + DXport;
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looping <= looping;
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end
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else
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begin
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Xoutport <= x_var ;
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Youtport <= y_var ;
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Uoutport <= u_var ;
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looping <= 1'b0;
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end
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end
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endmodule
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