99 lines
2.9 KiB
C++
99 lines
2.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#ifndef VERILOG_FRONTEND_H
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#define VERILOG_FRONTEND_H
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#include "kernel/yosys.h"
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#include "frontends/ast/ast.h"
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#include <stdio.h>
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#include <stdint.h>
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#include <list>
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_FRONTEND
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{
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// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
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extern struct AST::AstNode *current_ast;
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// this function converts a Verilog constant to an AST_CONSTANT node
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AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
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// state of `default_nettype
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extern bool default_nettype_wire;
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// running in SystemVerilog mode
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extern bool sv_mode;
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// running in -formal mode
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extern bool formal_mode;
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// running in -noassert mode
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extern bool noassert_mode;
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// running in -noassume mode
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extern bool noassume_mode;
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// running in -norestrict mode
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extern bool norestrict_mode;
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// running in -assume-asserts mode
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extern bool assume_asserts_mode;
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// running in -assert-assumes mode
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extern bool assert_assumes_mode;
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// running in -lib mode
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extern bool lib_mode;
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// running in -specify mode
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extern bool specify_mode;
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// lexer input stream
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extern std::istream *lexin;
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}
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// the pre-processor
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std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map,
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dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs);
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YOSYS_NAMESPACE_END
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// the usual bison/flex stuff
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extern int frontend_verilog_yydebug;
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int frontend_verilog_yylex(void);
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void frontend_verilog_yyerror(char const *fmt, ...);
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void frontend_verilog_yyrestart(FILE *f);
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int frontend_verilog_yyparse(void);
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int frontend_verilog_yylex_destroy(void);
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int frontend_verilog_yyget_lineno(void);
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void frontend_verilog_yyset_lineno (int);
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#endif
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