|
<pin_constraints>
|
|
<!-- For a given .blif file, we want to assign
|
|
- the clk0 signal to the clk[0] port of the FPGA fabric
|
|
- the clk1 signal to the clk[1] port of the FPGA fabric
|
|
-->
|
|
<set_io pin="clk[0]" net="clk0"/>
|
|
<set_io pin="clk[1]" net="clk1"/>
|
|
</pin_constraints>
|
|
|