64 lines
2.1 KiB
Verilog
Executable File
64 lines
2.1 KiB
Verilog
Executable File
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/*--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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-- File Name : diffeq.v
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-- Author(s) : P. Sridhar
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-- Affiliation : Laboratory for Digital Design Environments
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-- Department of Electrical & Computer Engineering
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-- University of Cincinnati
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-- Date Created : June 1991.
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-- Introduction : Behavioral description of a differential equation
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-- solver written in a synthesizable subset of VHDL.
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-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
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-- Obtained from the Highlevel Synthesis Workshop
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-- Repository.
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--
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-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
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-- Date Modified : Sept, 91.
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--
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-- Disclaimer : This comes with absolutely no guarantees of any
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-- kind (just stating the obvious ...)
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--
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-- Acknowledgement : The Distributed Synthesis Systems research at
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-- the Laboratory for Digital Design Environments,
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-- University of Cincinnati, is sponsored in part
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-- by the Defense Advanced Research Projects Agency
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-- under order number 7056 monitored by the Federal
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-- Bureau of Investigation under contract number
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-- J-FBI-89-094.
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--
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--------------------------------------------------------------------------
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-------------------------------------------------------------------------*/
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module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
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input clk;
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input reset;
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input [31:0]aport;
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input [31:0]dxport;
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output [31:0]xport;
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output [31:0]yport;
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output [31:0]uport;
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reg [31:0]xport;
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reg [31:0]yport;
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reg [31:0]uport;
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wire [31:0]temp;
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assign temp = uport * dxport;
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always @(posedge clk )
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begin
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if (reset == 1'b1)
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begin
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xport <= 0;
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yport <= 0;
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uport <= 0;
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end
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else
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if (xport < aport)
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begin
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xport <= xport + dxport;
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yport <= yport + temp;//(uport * dxport);
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uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
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end
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end
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endmodule
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