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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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e3f8a6cf7a
OpenFPGA
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openfpga_flow
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benchmarks
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micro_benchmark
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adder_8
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tangxifan
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
..
adder_8.act
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
adder_8.eblif
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
adder_8.v
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
adder_8_out.v
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00