170 lines
6.5 KiB
C++
170 lines
6.5 KiB
C++
/*********************************************************************
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* This function includes the writer for generating exchangeable
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* information, in order to interface different simulators
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********************************************************************/
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#include <cmath>
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#include <ctime>
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#include <map>
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#define MINI_CASE_SENSITIVE
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#include "ini.h"
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_scale.h"
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#include "simulation_utils.h"
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#include "verilog_constants.h"
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#include "verilog_simulation_info_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Top-level function to write an ini file which contains exchangeable
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* information, in order to interface different Verilog simulators
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********************************************************************/
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void print_verilog_simulation_info(
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const std::string& ini_fname, const VerilogTestbenchOption& options,
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const std::string& circuit_name, const std::string& src_dir,
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const AtomContext& atom_ctx, const PlacementContext& place_ctx,
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const IoLocationMap& io_location_map, const ModuleManager& module_manager,
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const e_config_protocol_type& config_protocol_type,
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const size_t& num_program_clock_cycles, const int& num_operating_clock_cycles,
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const float& prog_clock_freq, const float& op_clock_freq) {
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std::string timer_message =
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std::string("Write exchangeable file containing simulation information '") +
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ini_fname + std::string("'");
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std::string ini_dir_path = format_dir_path(find_path_dir_name(ini_fname));
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/* Create directories */
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create_directory(ini_dir_path);
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/* Start time count */
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Use default name if user does not provide one */
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VTR_ASSERT(true != ini_fname.empty());
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mINI::INIStructure ini;
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/* Compute simulation time period: full testbench and pre-configured testbench
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* has different length Currently, we only support the two types. And one of
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* them must be enabled when outputting this file
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*/
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float simulation_time_period = 0.;
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if (options.print_top_testbench()) {
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simulation_time_period = find_simulation_time_period(
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options.time_unit(), num_program_clock_cycles, 1. / prog_clock_freq,
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num_operating_clock_cycles, 1. / op_clock_freq);
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} else {
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VTR_ASSERT(options.print_preconfig_top_testbench());
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simulation_time_period = find_operating_phase_simulation_time(
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num_operating_clock_cycles, 1. / op_clock_freq, options.time_unit());
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}
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/* Identify the testbench file name depending on the type */
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std::string top_tb_name;
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if (options.print_top_testbench()) {
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top_tb_name =
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circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
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} else {
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VTR_ASSERT(options.print_preconfig_top_testbench());
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top_tb_name =
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circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
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}
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/* Basic information */
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ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
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ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
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ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name;
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ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
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ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit());
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ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
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ini["SIMULATION_DECK"]["VERILOG_FILE1"] =
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std::string(DEFINES_VERILOG_FILE_NAME);
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ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(
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circuit_name +
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std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
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ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] =
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std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);
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/* Information required by UVM */
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if (CONFIG_MEM_FRAME_BASED == config_protocol_type) {
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/* Find the top_module */
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ModuleId top_module =
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module_manager.find_module(generate_fpga_top_module_name());
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Address port */
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ModulePortId addr_port_id = module_manager.find_module_port(
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top_module, std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort addr_port = module_manager.module_port(top_module, addr_port_id);
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ini["SIMULATION_DECK"]["ADDR_WIDTH"] =
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std::to_string(addr_port.get_width());
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/* I/O port */
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std::vector<BasicPort> module_io_ports =
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module_manager.module_ports_by_type(top_module,
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ModuleManager::MODULE_GPIO_PORT);
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size_t total_gpio_width = 0;
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for (const BasicPort& module_io_port : module_io_ports) {
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total_gpio_width += module_io_port.get_width();
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}
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ini["SIMULATION_DECK"]["GPIO_WIDTH"] = std::to_string(total_gpio_width);
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/* I/O direction map:
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* - '0' output
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* - '1' input
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* For unused ports, by default we assume it is configured as inputs
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* TODO: this should be reworked to be consistent with bitstream
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*/
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for (const BasicPort& module_io_port : module_manager.module_ports_by_type(
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top_module, ModuleManager::MODULE_GPIO_PORT)) {
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std::string io_direction(module_io_port.get_width(), '1');
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for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
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/* Bypass non-I/O atom blocks ! */
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if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) &&
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(AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk))) {
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continue;
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}
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/* Find the index of the mapped GPIO in top-level FPGA fabric */
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size_t io_index = io_location_map.io_index(
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile,
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module_io_port.get_name());
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if (size_t(-1) == io_index) {
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continue;
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}
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if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
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io_direction[io_index] = '1';
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} else {
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VTR_ASSERT(AtomBlockType::OUTPAD ==
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atom_ctx.nlist.block_type(atom_blk));
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io_direction[io_index] = '0';
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}
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std::string io_tag = "IO" + module_io_port.get_name();
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/* Organize the vector to string */
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ini["SIMULATION_DECK"][io_tag] = io_direction;
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}
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}
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}
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mINI::INIFile file(ini_fname);
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file.generate(ini, true);
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}
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} /* end namespace openfpga */
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