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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice
History
AurelienUoU 213f94ddee Correct preconfiguration 2019-01-31 16:43:47 -07:00
..
base fix a bug for supporting default circuit_model of LUTs and FFs 2019-01-10 15:10:05 -07:00
clb_pin_remap rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
spice fixa bug in determining mux structure 2019-01-22 13:54:50 -07:00
verilog Correct preconfiguration 2019-01-31 16:43:47 -07:00