riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/tasks
History
tangxifan a83bc3f75c [Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI 2020-09-21 17:38:16 -06:00
..
basic_tests enrich basic regression tests to cover more critical microbenchmarks 2020-07-27 19:47:43 -06:00
benchmark_sweep update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
compilation_verification/config update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
fpga_bitstream add regression test to track runtime on big fpga devices using practical benchmarks 2020-07-28 12:38:42 -06:00
fpga_sdc/sdc_time_unit/config classify regression test to dedicated categories 2020-07-27 17:18:59 -06:00
fpga_spice/generate_spice/config add load architecture bitstream test case and reorganize regression tests in category of openfpga tools 2020-07-27 15:54:46 -06:00
fpga_verilog [Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI 2020-09-21 17:38:16 -06:00
mcnc_big20/config update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md add README to explain the organization of regression tests 2020-07-28 13:44:06 -06:00
generate_testbenches Reorganize task directory 2020-07-04 19:06:41 -06:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

Please keep this README up-to-date on the OpenFPGA tools