tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix		2019-09-18 15:04:51 -06:00
..
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
arch	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00
benchmarks	Added Test Modes - Added blif VPR Option	2019-08-22 17:00:59 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Separated Modelsim tcl script generation	2019-09-07 12:36:22 -04:00
scripts	Added explicit checking to VVP execution	2019-09-18 12:14:26 -06:00
tasks	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00