205 lines
8.6 KiB
C++
205 lines
8.6 KiB
C++
/************************************************
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* Header file for verilog_writer_utils.cpp
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* Include function declaration for most frequently
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* used Verilog writers
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***********************************************/
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#ifndef VERILOG_WRITER_UTILS_H
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#define VERILOG_WRITER_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include <string>
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#include <vector>
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#include "circuit_library.h"
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#include "module_manager.h"
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#include "openfpga_port.h"
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#include "verilog_port_types.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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/* Tips: for naming your function in this header/source file
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* If a function outputs to a file, its name should begin with "print_verilog"
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* If a function creates a string without outputting to a file, its name should
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* begin with "generate_verilog" Please show respect to this naming convention,
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* in order to keep a clean header/source file as well maintain a easy way to
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* identify the functions
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*/
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void print_verilog_default_net_type_declaration(
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std::fstream& fp, const e_verilog_default_net_type& default_net_type);
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void print_verilog_file_header(std::fstream& fp, const std::string& usage,
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const bool& include_time_stamp,
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const bool& include_time_scale = false);
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void print_verilog_include_netlist(std::fstream& fp,
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const std::string& netlist_name);
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void print_verilog_define_flag(std::fstream& fp, const std::string& flag_name,
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const int& flag_value);
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void print_verilog_include_defines_preproc_file(std::fstream& fp,
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const std::string& verilog_dir);
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void print_verilog_comment(std::fstream& fp, const std::string& comment);
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void print_verilog_preprocessing_flag(std::fstream& fp,
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const std::string& preproc_flag);
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void print_verilog_endif(std::fstream& fp);
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void print_verilog_module_definition(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id);
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void print_verilog_module_ports(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& module_id,
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const e_verilog_default_net_type& default_net_type);
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void print_verilog_module_declaration(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& module_id,
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const e_verilog_default_net_type& default_net_type);
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void print_verilog_module_instance(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& module_id, const std::string& instance_name,
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const std::map<std::string, BasicPort>& port2port_name_map,
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const bool& use_explicit_port_map);
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void print_verilog_module_instance(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& parent_module_id, const ModuleId& child_module_id,
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const std::map<std::string, BasicPort>& port2port_name_map,
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const bool& use_explicit_port_map);
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void print_verilog_module_end(
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std::fstream& fp, const std::string& module_name,
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const e_verilog_default_net_type& default_net_type);
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std::string generate_verilog_port(
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const enum e_dump_verilog_port_type& dump_port_type,
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const BasicPort& port_info, const bool& must_print_port_size = true,
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const bool& big_endian = true);
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bool two_verilog_ports_mergeable(const BasicPort& portA,
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const BasicPort& portB);
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BasicPort merge_two_verilog_ports(const BasicPort& portA,
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const BasicPort& portB);
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std::vector<BasicPort> combine_verilog_ports(
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const std::vector<BasicPort>& ports);
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std::string generate_verilog_ports(const std::vector<BasicPort>& merged_ports);
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BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports,
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const std::string& bus_port_name);
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std::string generate_verilog_local_wire(
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const BasicPort& output_port, const std::vector<BasicPort>& input_ports);
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std::string generate_verilog_constant_values(
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const std::vector<size_t>& const_values, const bool& short_constant = true);
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std::string generate_verilog_port_constant_values(
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const BasicPort& output_port, const std::vector<size_t>& const_values,
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const bool& is_register = false);
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std::string generate_verilog_ports_constant_values(
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const std::vector<BasicPort>& output_ports,
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const std::vector<size_t>& const_values, const bool& is_register = false);
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void print_verilog_wire_constant_values(
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std::fstream& fp, const BasicPort& output_port,
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const std::vector<size_t>& const_values);
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void print_verilog_deposit_wire_constant_values(
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std::fstream& fp, const BasicPort& output_port,
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const std::vector<size_t>& const_values);
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void print_verilog_force_wire_constant_values(
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std::fstream& fp, const BasicPort& output_port,
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const std::vector<size_t>& const_values);
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void print_verilog_wire_connection(std::fstream& fp,
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const BasicPort& output_port,
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const BasicPort& input_port,
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const bool& inverted);
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void print_verilog_register_connection(std::fstream& fp,
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const BasicPort& output_port,
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const BasicPort& input_port,
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const bool& inverted);
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void print_verilog_buffer_instance(std::fstream& fp,
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ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const ModuleId& parent_module_id,
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const CircuitModelId& buffer_model,
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const BasicPort& instance_input_port,
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const BasicPort& instance_output_port);
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void print_verilog_local_sram_wires(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& sram_model,
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const e_config_protocol_type sram_orgz_type,
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const size_t& port_size);
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void print_verilog_local_config_bus(
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std::fstream& fp, const std::string& prefix,
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const e_config_protocol_type& sram_orgz_type, const size_t& instance_id,
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const size_t& num_conf_bits);
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void print_verilog_mux_config_bus(
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std::fstream& fp, const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model, const e_config_protocol_type& sram_orgz_type,
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const size_t& mux_size, const size_t& mux_instance_id,
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const size_t& num_reserved_conf_bits, const size_t& num_conf_bits);
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void print_verilog_formal_verification_mux_sram_ports_wiring(
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std::fstream& fp, const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model, const size_t& mux_size,
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const size_t& mux_instance_id, const size_t& num_conf_bits,
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const BasicPort& fm_config_bus);
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void print_verilog_shifted_clock_stimuli(std::fstream& fp,
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const BasicPort& port,
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const float& initial_delay,
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const float& pulse_width,
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const size_t& initial_value);
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void print_verilog_pulse_stimuli(std::fstream& fp, const BasicPort& port,
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const size_t& initial_value,
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const float& pulse_width,
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const size_t& flip_value);
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void print_verilog_pulse_stimuli(std::fstream& fp, const BasicPort& port,
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const size_t& initial_value,
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const std::vector<float>& pulse_widths,
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const std::vector<size_t>& flip_values,
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const std::string& wait_condition);
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void print_verilog_clock_stimuli(std::fstream& fp, const BasicPort& port,
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const size_t& initial_value,
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const float& pulse_width,
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const std::string& wait_condition);
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void print_verilog_netlist_include_header_file(
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const std::vector<std::string>& netlists_to_be_included,
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const char* subckt_dir, const char* header_file_name,
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const bool& include_time_stamp);
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} /* end namespace openfpga */
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#endif
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