159 lines
4.7 KiB
ReStructuredText
159 lines
4.7 KiB
ReStructuredText
.. _file_formats_fabric_bitstream:
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Fabric-dependent Bitstream
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--------------------------
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.. _file_formats_fabric_bitstream_plain_text:
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Plain text (.bit)
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~~~~~~~~~~~~~~~~~
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This file format is designed to be directly loaded to an FPGA fabric.
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It does not include any comments but only bitstream.
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The information depends on the type of configuration procotol.
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.. option:: vanilla
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A line consisting of ``0`` | ``1``
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.. option:: scan_chain
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Multiple lines consisting of ``0`` | ``1``
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For example, a bitstream for 1 configuration regions:
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.. code-block:: xml
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0
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1
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0
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0
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For example, a bitstream for 4 configuration regions:
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.. code-block:: xml
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0000
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1010
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0110
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0120
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.. note:: When there are multiple configuration regions, each line may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: memory_bank
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Multiple lines will be included, each of which is organized as <bl_address><wl_address><bits>.
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The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <bl_address 5 bits><wl_address 5 bits><data input 1 bits>
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The first part represents the Bit-Line address.
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The second part represents the Word-Line address.
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The third part represents the configuration bit.
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For example
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.. code-block:: xml
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<bitline_address><wordline_address><bit_value>
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<bitline_address><wordline_address><bit_value>
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...
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<bitline_address><wordline_address><bit_value>
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: frame_based
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Multiple lines will be included, each of which is organized as ``<address><data_input_bits>``.
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The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <address 14 bits><data input 1 bits>
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Note that the address may include don't care bit which is denoted as ``x``.
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.. note:: OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
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For example
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.. code-block:: xml
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<frame_address><bit_value>
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<frame_address><bit_value>
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...
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<frame_address><bit_value>
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. _file_formats_fabric_bitstream_xml:
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XML (.xml)
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~~~~~~~~~~
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This file format is designed to generate testbenches using external tools, e.g., CocoTB.
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In principle, the file consist a number of XML node ``<region>``, each region has a unique id, and contains a number of XML nodes ``<bit>``.
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- ``id``: The unique id of a configuration region in the fabric bitstream.
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A quick example:
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.. code-block:: xml
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<region id="0">
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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</bit>
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</region>
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Each XML node ``<bit>`` contains the following attributes:
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- ``id``: The unique id of the configuration bit in the fabric bitstream.
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- ``value``: The configuration bit value.
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- ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
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A quick example:
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.. code-block:: xml
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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</bit>
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Other information may depend on the type of configuration procotol.
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.. option:: memory_bank
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- ``bl``: Bit line address information
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- ``wl``: Word line address information
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A quick example:
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.. code-block:: xml
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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<bl address="000000"/>
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<wl address="000000"/>
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</bit>
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.. option:: frame_based
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- ``frame``: frame address information
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.. note:: Frame address may include don't care bit which is denoted as ``x``.
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A quick example:
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.. code-block:: xml
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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<frame address="0001000x00000x01"/>
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</bit>
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