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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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dc11e84f6a
OpenFPGA
/
openfpga_flow
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tasks
/
fpga_verilog
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thru_channel
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tangxifan
6c925dcded
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00
..
thru_narrow_tile
/config
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00
thru_wide_tile
/config
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00