tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks		2019-09-27 13:51:22 -06:00
..
base	refactoring the configuration bus Verilog generation for MUXes	2019-09-27 11:47:34 -06:00
bitstream	replace spice_models with circuit model in bitstream generator	2019-08-16 16:36:49 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	Refactored Verilog wiring for formal verification ports in Switch Blocks	2019-09-27 13:51:22 -06:00