tangxifan 97b089ae3c [test] added new testcases to validate fpga core wrapper		2023-06-18 21:01:37 -07:00
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configuration_chain/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
configuration_chain_config_done_io/config	[Test] Update test case by using GPIO with config_done signals	2022-02-24 09:49:34 -08:00
configuration_chain_no_time_stamp/config	[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp	2022-01-25 16:41:36 -08:00
configuration_frame/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
flatten_memory/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
fpga_core_wrapper/config	[test] added new testcases to validate fpga core wrapper	2023-06-18 21:01:37 -07:00
memory_bank/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
preconfigured_testbench_without_self_checking/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00