39 lines
849 B
YAML
39 lines
849 B
YAML
name: Cell Library Tests
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# Run CI on push, PR, and weekly.
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on:
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push:
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pull_request:
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schedule:
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- cron: "0 0 * * 0 " # weekly
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# Multiple job to tests
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jobs:
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# Test the RTL compilation compatibility
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verilog:
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name: RTL compilation and tests
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runs-on: ubuntu-20.04
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steps:
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- name: Cancel previous
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uses: styfle/cancel-workflow-action@0.9.1
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with:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v3
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- name: Install Dependencies
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run: |
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sudo bash .github/workflows/install_dependencies_run.sh
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- name: Dump tool versions
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run: |
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iverilog -V
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vvp -V
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- name: Verilog compilation
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run: |
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cd openfpga_flow/openfpga_cell_library
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make compile_verilog
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