OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice/verilog
tangxifan 861c449606 support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
..
verilog_api.c clean up codes 2018-09-27 14:26:08 -06:00
verilog_api.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_decoder.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_decoder.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_global.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_global.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_lut.c support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
verilog_lut.h support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
verilog_pbtypes.c support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
verilog_pbtypes.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_primitives.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_primitives.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_routing.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_routing.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_submodules.c fix a bug in tapbuf 2018-09-21 19:00:22 -06:00
verilog_submodules.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_top_netlist.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_top_netlist.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_utils.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_utils.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00