39 lines
3.1 KiB
Markdown
39 lines
3.1 KiB
Markdown
# Naming convention for OpenFPGA architecture files
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Please reveal the following architecture features in the names to help quickly spot architecture files.
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Note that an OpenFPGA architecture can be applied to multiple VPR architecture files.
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- k<lut\_size>\_<frac><Native>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
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* The keyword 'frac' is to specify if fracturable LUT is used or not.
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* The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
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- N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
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- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered
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- adder\_chain: If hard adder/carry chain is used inside CLBs
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- register\_chain: If shift register chain is used inside CLBs
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- scan\_chain: If scan chain testing infrastructure is used inside CLBs
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- <wide>\_<frac>\_dsp<dsp\_size>reg: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here.
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- The keyword 'wide' is to specify if the DSP spans more than 1 column.
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- The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
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- The keyword 'reg' is to specify if the DSP has input and output registers. If only input or output registers are used, the keyword will be 'regin' or 'regout' respectively.
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- mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
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- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
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- <bank\|cc\|frame\|standalone>: specify the type of configuration protocol used in the architecture.
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- `bank` refers to the memory bank
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- `cc` refers to the configuration chain
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- `frame` refers to the frame-based organization
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- `standalone` referes to the vanilla organization
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- fixed\_sim: fixed clock frequencies in simulation settings. If auto clock frequencies are used, there is no need to appear in the naming
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- intermediate buffer: If intermediate buffers are used in LUT designs.
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- behavioral: If behavioral Verilog modeling is specified
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- local\_encoder: If local encoders are used in routing multiplexer design
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- spyio/spypad: If spy I/Os are used
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- registerable\_io: If I/Os are registerable (can be either combinational or sequential)
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- stdcell: If circuit designs are built with standard cells only
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- tree\_mux: If routing multiplexers are built with a tree-like structure
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- <feature_size>: The technology node which the delay numbers are extracted from.
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- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
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- GlobalTile<Int>Clk<Pin>: How many clocks are defined through global ports from physical tiles.
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* <Int> is the number of clocks
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* <Pin> When specified, multiple clocks are in separated pins with different names
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Other features are used in naming should be listed here.
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