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verilog_api.c
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
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verilog_api.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_autocheck_top_testbench.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_autocheck_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_compact_netlist.c
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
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verilog_compact_netlist.h
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
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verilog_decoder.c
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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verilog_decoder.h
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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verilog_formal_random_top_testbench.c
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
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verilog_formal_random_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_formality_autodeck.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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verilog_formality_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_global.c
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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verilog_global.h
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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verilog_include_netlists.c
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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verilog_include_netlists.h
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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verilog_modelsim_autodeck.c
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_modelsim_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_pbtypes.c
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Avoid configuration bits for module wihch don't require them
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2019-06-20 09:40:41 -06:00 |
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verilog_pbtypes.h
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support bus explicit port mapping to standard cells (for BRAMs)
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2019-06-14 11:09:15 -06:00 |
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verilog_primitives.c
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support bus explicit port mapping to standard cells (for BRAMs)
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2019-06-14 11:09:15 -06:00 |
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verilog_primitives.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_report_timing.c
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Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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verilog_report_timing.h
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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verilog_routing.c
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fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
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verilog_routing.h
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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verilog_sdc.c
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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verilog_sdc.h
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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verilog_sdc_pb_types.c
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Break memories even in the clb sdc
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2019-06-16 14:27:29 -06:00 |
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verilog_sdc_pb_types.h
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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verilog_submodules.c
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
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verilog_submodules.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_tcl_utils.c
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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verilog_tcl_utils.h
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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verilog_top_netlist_utils.c
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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verilog_top_netlist_utils.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_top_testbench.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_utils.c
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fix a bug in formal verification port for memory bank configuration circuits
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2019-06-13 15:33:13 -06:00 |
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verilog_utils.h
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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verilog_verification_top_netlist.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_verification_top_netlist.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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