236 lines
6.2 KiB
C++
236 lines
6.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthGowinPass : public ScriptPass
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{
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SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_gowin [options]\n");
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log("\n");
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log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -vout <file>\n");
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log(" write the design to the specified Verilog netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use BRAM cells in output netlist\n");
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log("\n");
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log(" -nodram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, vout_file;
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bool retime, nobram, nodram, flatten, nodffe;
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void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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vout_file = "";
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retime = false;
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flatten = true;
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nobram = false;
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nodffe = false;
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nodram = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-vout" && argidx+1 < args.size()) {
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vout_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nodram") {
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nodram = true;
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continue;
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}
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if (args[argidx] == "-nodffe") {
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_GOWIN pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/gowin/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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}
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/gowin/bram.txt");
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run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
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}
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if (!nodram && check_label("dram", "(skip if -nodram)"))
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{
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run("memory_bram -rules +/gowin/dram.txt");
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run("techmap -map +/gowin/drams_map.v");
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run("determine_init");
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}
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if (check_label("fine"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
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run("techmap -map +/techmap.v");
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if (retime || help_mode)
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run("abc -dff", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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{
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run("dffsr2dff");
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run("dff2dffs");
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run("opt_clean");
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if (!nodffe)
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run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
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run("techmap -map +/gowin/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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}
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if (check_label("map_luts"))
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{
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run("abc -lut 4");
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/gowin/cells_map.v");
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run("hilomap -hicell VCC V -locell GND G");
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run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
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run("dffinit -ff DFF Q INIT");
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run("clean");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("vout"))
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{
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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}
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}
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} SynthGowinPass;
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PRIVATE_NAMESPACE_END
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