134 lines
5.0 KiB
Bash
134 lines
5.0 KiB
Bash
# python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
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# ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
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# --top_module s298 \
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# --power \
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# --power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \
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# --min_route_chan_width 1.3 \
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# --vpr_fpga_verilog \
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# --vpr_fpga_verilog_dir . \
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# --vpr_fpga_x2p_rename_illegal_port \
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# --end_flow_with_test \
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# --vpr_fpga_verilog_include_icarus_simulator \
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# --vpr_fpga_verilog_formal_verification_top_netlist \
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# --vpr_fpga_verilog_include_timing \
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# --vpr_fpga_verilog_include_signal_init \
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# --vpr_fpga_verilog_print_autocheck_top_testbench
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# Test popular multi-mode architecture
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
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./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
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--fpga_flow vpr_blif \
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--top_module test_modes \
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--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
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--power \
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--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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#--fix_route_chan_width 300 \
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir . \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_include_icarus_simulator \
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--vpr_fpga_verilog_formal_verification_top_netlist \
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--vpr_fpga_verilog_include_timing \
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--vpr_fpga_verilog_include_signal_init \
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--vpr_fpga_verilog_print_autocheck_top_testbench \
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--debug \
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--vpr_fpga_bitstream_generator \
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--vpr_fpga_verilog_print_user_defined_template \
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--vpr_fpga_verilog_print_report_timing_tcl \
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--vpr_fpga_verilog_print_sdc_pnr \
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--vpr_fpga_verilog_print_sdc_analysis \
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--vpr_fpga_x2p_compact_routing_hierarchy \
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--end_flow_with_test
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# Test Standard cell MUX2
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
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./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
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--fpga_flow vpr_blif \
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--top_module test_modes \
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--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
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--power \
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--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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#--fix_route_chan_width 300 \
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir . \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_include_icarus_simulator \
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--vpr_fpga_verilog_formal_verification_top_netlist \
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--vpr_fpga_verilog_include_timing \
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--vpr_fpga_verilog_include_signal_init \
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--vpr_fpga_verilog_print_autocheck_top_testbench \
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--debug \
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--vpr_fpga_bitstream_generator \
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--vpr_fpga_verilog_print_user_defined_template \
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--vpr_fpga_verilog_print_report_timing_tcl \
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--vpr_fpga_verilog_print_sdc_pnr \
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--vpr_fpga_verilog_print_sdc_analysis \
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--vpr_fpga_x2p_compact_routing_hierarchy \
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--end_flow_with_test
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# Test local encoder feature
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
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./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
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--fpga_flow vpr_blif \
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--top_module test_modes \
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--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
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--power \
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--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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--fix_route_chan_width 300 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir . \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_include_icarus_simulator \
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--vpr_fpga_verilog_formal_verification_top_netlist \
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--vpr_fpga_verilog_include_timing \
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--vpr_fpga_verilog_include_signal_init \
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--vpr_fpga_verilog_print_autocheck_top_testbench \
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--debug \
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--vpr_fpga_bitstream_generator \
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--vpr_fpga_verilog_print_user_defined_template \
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--vpr_fpga_verilog_print_report_timing_tcl \
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--vpr_fpga_verilog_print_sdc_pnr \
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--vpr_fpga_verilog_print_sdc_analysis \
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--vpr_fpga_x2p_compact_routing_hierarchy \
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--end_flow_with_test
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# Test tileable routing feature
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#python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \
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#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
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#--fpga_flow vpr_blif \
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#--top_module test_modes \
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#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
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#--power \
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#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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##--fix_route_chan_width 300 \
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#--min_route_chan_width 1.3 \
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#--vpr_fpga_verilog \
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#--vpr_fpga_verilog_dir . \
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#--vpr_fpga_x2p_rename_illegal_port \
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#--vpr_fpga_verilog_include_icarus_simulator \
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#--vpr_fpga_verilog_formal_verification_top_netlist \
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#--vpr_fpga_verilog_include_timing \
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#--vpr_fpga_verilog_include_signal_init \
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#--vpr_fpga_verilog_print_autocheck_top_testbench \
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#--debug \
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#--vpr_fpga_bitstream_generator \
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#--vpr_fpga_verilog_print_user_defined_template \
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#--vpr_fpga_verilog_print_report_timing_tcl \
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#--vpr_fpga_verilog_print_sdc_pnr \
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#--vpr_fpga_verilog_print_sdc_analysis \
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#--vpr_fpga_x2p_compact_routing_hierarchy \
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#--vpr_use_tileable_route_chan_width \
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#--end_flow_with_test
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