tangxifan ce6018e123 [Arch] Enriched DFF model to support active-low/high FFs		2021-04-21 22:48:31 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs	2021-04-21 14:03:51 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping	2021-04-21 19:50:07 -06:00
openfpga_arch	[Arch] Enriched DFF model to support active-low/high FFs	2021-04-21 22:48:31 -06:00
openfpga_cell_library	[HDL] Rename multi-mode DFF module	2021-04-21 20:06:03 -06:00
openfpga_shell_scripts	[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting	2021-04-19 16:15:25 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[HDL] Add technology library for customizable DFF synthesis	2021-04-21 19:50:51 -06:00
regression_test_scripts	[Test] Patch regression tests for fpga bitstream	2021-04-19 17:15:14 -06:00
scripts	[Script] Add tolerance options to check qor script	2021-03-23 12:26:33 -06:00
tasks	[Test] Update IWLS test by using new architecture and customize DFF techmap	2021-04-21 19:51:25 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Enriched DFF model to support active-low/high FFs	2021-04-21 22:48:31 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00