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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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cc7adae91e
OpenFPGA
/
openfpga
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tangxifan
e6c896d583
now inout must be global port and I/O port so that it will appear in the top-level module
2020-04-08 16:54:08 -06:00
..
src
now inout must be global port and I/O port so that it will appear in the top-level module
2020-04-08 16:54:08 -06:00
test_blif
add missing files for micro benchmarks
2020-03-20 11:08:55 -06:00
test_openfpga_arch
now inout must be global port and I/O port so that it will appear in the top-level module
2020-04-08 16:54:08 -06:00
test_script
openfpga shell now support continued line charactor '\'
2020-04-07 21:27:51 -06:00
test_vpr_arch
bug fixed in register scan-chain architecture
2020-04-07 17:06:16 -06:00
CMakeLists.txt
add simulation ini file writer
2020-02-27 18:01:47 -07:00