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OpenFPGA/openfpga_flow/openfpga_cell_library/verilog
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tangxifan 722a9bcf63 [HDL] Add scan-chain DFF cell with configuration enable signal 2021-01-04 14:31:26 -07:00
..
adder.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
aib.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dff.v [HDL] Add scan-chain DFF cell with configuration enable signal 2021-01-04 14:31:26 -07:00
dpram.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram1k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram16k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
frac_mem_32k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
gpio.v [HDL] Add new gpio cell with protection circuitry 2020-11-30 17:52:39 -07:00
latch.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
lut6.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_32x32.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_36x36.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mux2.v [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
sram.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00