129 lines
4.0 KiB
C
129 lines
4.0 KiB
C
/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include spice support headers*/
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#include "read_xml_spice_util.h"
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#include "linkedlist.h"
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#include "fpga_spice_globals.h"
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#include "spice_globals.h"
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#include "fpga_spice_utils.h"
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#include "spice_subckt.h"
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#include "spice_pbtypes.h"
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#include "spice_heads.h"
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#include "spice_lut.h"
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#include "spice_top_netlist.h"
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#include "spice_mux_testbench.h"
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#include "spice_grid_testbench.h"
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#include "spice_lut_testbench.h"
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#include "spice_hardlogic_testbench.h"
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#include "spice_routing_testbench.h"
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static char* run_hspice_shell_script_name = "run_hspice_sim.sh";
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static char* sim_results_dir_name = "results/";
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void fprint_run_hspice_shell_script(t_spice spice,
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char* spice_dir_path,
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char* subckt_dir_path) {
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FILE* fp = NULL;
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/* Format the directory path */
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char* spice_dir_formatted = format_dir_path(spice_dir_path);
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char* shell_script_path = my_strcat(spice_dir_path, run_hspice_shell_script_name);
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char* testbench_file = NULL;
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char* chomped_testbench_file = NULL;
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char* chomped_testbench_path = NULL;
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char* chomped_testbench_name = NULL;
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char* sim_results_dir_path = my_strcat(spice_dir_formatted, sim_results_dir_name);
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t_llist* temp = tb_head;
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int progress_cnt = 0;
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int total_num_sim = 0;
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int num_sim_clock_cycle = 0;
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create_dir_path(sim_results_dir_path);
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/* Check if the path exists*/
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fp = fopen(shell_script_path,"w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Shell Script for running HSPICE %s!",__FILE__, __LINE__, shell_script_path);
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exit(1);
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}
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/* Go to the subckt dir for HSPICE VerilogA sim*/
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/* For VerilogA initilization */
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if (1 == rram_design_tech) {
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fprintf(fp, "cd %s\n", subckt_dir_path);
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fprintf(fp, "source /uusoc/facility/cad_common/Synopsys/hspice_vM-2017.03/hspice/bin/cshrc.meta\n");
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}
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total_num_sim = 0;
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temp = tb_head;
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while(temp) {
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total_num_sim++;
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temp = temp->next;
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}
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progress_cnt = 0;
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temp = tb_head;
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/* Run hspice lut testbench netlist */
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while(temp) {
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testbench_file = ((t_spicetb_info*)(temp->dptr))->tb_name;
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num_sim_clock_cycle = ((t_spicetb_info*)(temp->dptr))->num_sim_clock_cycles;
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chomped_testbench_file = chomp_file_name_postfix(testbench_file);
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split_path_prog_name(chomped_testbench_file,'/',&chomped_testbench_path ,&chomped_testbench_name);
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fprintf(fp, "echo Number of clock cycles in simulation: %d\n", num_sim_clock_cycle);
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fprintf(fp, "echo Simulation progress: %d Finish, %d to go, total %d\n",
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progress_cnt, total_num_sim-progress_cnt, total_num_sim);
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progress_cnt++;
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fprintf(fp, "hspice64 -mt %d -i %s -o %s%s.lis ",
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spice_sim_multi_thread_num,
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testbench_file, sim_results_dir_path, chomped_testbench_name);
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temp = temp->next;
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if (1 == rram_design_tech) {
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fprintf(fp, "-hdlpath /uusoc/facility/cad_common/Synopsys/hspice_vM-2017.03/hspice/include\n");
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} else {
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fprintf(fp, "\n");
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}
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}
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fprintf(fp, "echo Simulation progress: %d Finish, %d to go, total %d\n",
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progress_cnt, total_num_sim-progress_cnt, total_num_sim);
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if (1 == rram_design_tech) {
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fprintf(fp, "cd %s\n", spice_dir_path);
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}
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/* close fp */
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fclose(fp);
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vpr_printf(TIO_MESSAGE_INFO,"Shell Script for running HSPICE (%s) has been created successfully!\n", shell_script_path);
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/* Free */
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my_free(spice_dir_formatted);
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my_free(shell_script_path);
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my_free(chomped_testbench_file);
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return;
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}
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