631 lines
26 KiB
C
631 lines
26 KiB
C
void my_free(void* ptr);
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char* my_gettime();
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char* format_dir_path(char* dir_path);
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int try_access_file(char* file_path);
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void my_remove_file(char* file_path);
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int create_dir_path(char* dir_path);
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char* my_strcat(char* str1,
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char* str2);
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int split_path_prog_name(char* prog_path,
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char split_token,
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char** ret_path,
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char** ret_prog_name);
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char* chomp_file_name_postfix(char* file_name);
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void fprint_commented_sram_bits(FILE* fp,
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int num_sram_bits, int* sram_bits);
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t_spice_model* find_name_matched_spice_model(char* spice_model_name,
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int num_spice_model,
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t_spice_model* spice_models);
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t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type,
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int num_spice_model,
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t_spice_model* spice_models);
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void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
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t_spice_model* spice_model);
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t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model,
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enum e_spice_model_port_type port_type,
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int* port_num, boolean ignore_global_port);
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t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model,
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enum e_spice_model_port_type port_type,
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int* port_num, boolean ignore_global_port);
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t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib,
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e_spice_trans_type trans_type);
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char* my_itoa(int input);
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char* fpga_spice_create_one_subckt_filename(char* file_name_prefix,
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int subckt_x, int subckt_y,
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char* file_name_postfix);
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char* chomp_spice_node_prefix(char* spice_node_prefix);
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char* format_spice_node_prefix(char* spice_node_prefix);
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t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,
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t_spice_model_port* spice_model_port);
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char* format_spice_node_prefix(char* spice_node_prefix);
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t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type,
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enum e_spice_model_port_type port_type,
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int* port_num);
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t_block* search_mapped_block(int x, int y, int z);
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int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model,
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int mux_size,
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int num_input_per_level,
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boolean special_basis);
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int determine_tree_mux_level(int mux_size);
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int determine_num_input_basis_multilevel_mux(int mux_size,
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int mux_level);
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int tree_mux_last_level_input_num(int num_level,
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int mux_size);
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int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit,
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int mux_size);
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int determine_lut_path_id(int lut_size,
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int* lut_inputs);
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int* decode_onelevel_mux_sram_bits(int fan_in,
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int mux_level,
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int path_id);
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int* decode_multilevel_mux_sram_bits(int fan_in,
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int mux_level,
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int path_id);
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int* decode_tree_mux_sram_bits(int fan_in,
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int mux_level,
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int path_id);
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void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model,
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int mux_size, int path_id,
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int* bit_len, int** conf_bits, int* mux_level);
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char** my_strtok(char* str,
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char* delims,
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int* len);
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int get_opposite_side(int side);
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char* convert_side_index_to_string(int side);
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char* convert_chan_type_to_string(t_rr_type chan_type);
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char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction);
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void init_spice_net_info(t_spice_net_info* spice_net_info);
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t_spice_model* find_iopad_spice_model(int num_spice_model,
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t_spice_model* spice_models);
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boolean is_grid_coordinate_in_range(int x_min,
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int x_max,
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int grid_x);
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char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type);
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int determine_io_grid_side(int x,
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int y);
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void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node,
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int* num_drive_rr_nodes,
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t_rr_node*** drive_rr_nodes,
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int** switch_indices);
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int find_path_id_prev_rr_node(int num_drive_rr_nodes,
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t_rr_node** drive_rr_nodes,
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t_rr_node* src_rr_node);
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int pb_pin_net_num(t_rr_node* pb_rr_graph,
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t_pb_graph_pin* pin);
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float pb_pin_density(t_rr_node* pb_rr_graph,
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t_pb_graph_pin* pin);
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float pb_pin_probability(t_rr_node* pb_rr_graph,
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t_pb_graph_pin* pin);
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int pb_pin_init_value(t_rr_node* pb_rr_graph,
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t_pb_graph_pin* pin);
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float get_rr_node_net_density(t_rr_node node);
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float get_rr_node_net_probability(t_rr_node node);
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int get_rr_node_net_init_value(t_rr_node node);
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int find_parent_pb_type_child_index(t_pb_type* parent_pb_type,
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int mode_index,
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t_pb_type* child_pb_type);
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void gen_spice_name_tag_pb_rec(t_pb* cur_pb,
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char* prefix);
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void gen_spice_name_tags_all_pbs();
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void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge);
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void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin);
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void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node);
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void update_one_grid_pack_prev_node_edge(int x, int y);
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void update_grid_pbs_post_route_rr_graph();
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int find_pb_mapped_logical_block_rec(t_pb* cur_pb,
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t_spice_model* pb_spice_model,
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char* pb_spice_name_tag);
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int find_grid_mapped_logical_block(int x, int y,
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t_spice_model* pb_spice_model,
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char* pb_spice_name_tag);
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void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node,
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int* num_inputs,
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int* num_outputs,
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int* num_clock_pins);
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void map_clb_pins_to_pb_graph_pins();
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int recommend_num_sim_clock_cycle();
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void auto_select_num_sim_clock_cycle(t_spice* spice,
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float signal_density_weight);
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void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model);
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void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model);
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void free_spice_model_grid_index_low_high(int num_spice_models,
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t_spice_model* spice_model);
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void update_one_spice_model_grid_index_low(int x, int y,
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t_spice_model* cur_spice_model);
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void update_spice_models_grid_index_low(int x, int y,
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int num_spice_models,
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t_spice_model* spice_model);
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void update_one_spice_model_grid_index_high(int x, int y,
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t_spice_model* cur_spice_model);
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void update_spice_models_grid_index_high(int x, int y,
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int num_spice_models,
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t_spice_model* spice_model);
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void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model);
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void zero_spice_model_grid_index_low_high(int num_spice_models,
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t_spice_model* spice_model);
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char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure);
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boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf);
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int find_pb_type_idle_mode_index(t_pb_type cur_pb_type);
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int find_pb_type_physical_mode_index(t_pb_type cur_pb_type);
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void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y);
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void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin,
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int mode_index);
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void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,
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int mode_index);
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void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,
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int mode_index);
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void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,
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int mode_index);
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void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node);
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void load_one_pb_graph_pin_temp_net_num_from_pb(t_pb* cur_pb,
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t_pb_graph_pin* cur_pb_graph_pin);
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void load_pb_graph_node_temp_net_num_from_pb(t_pb* cur_pb);
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void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_pb* cur_pb);
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void update_pb_vpack_net_num_from_temp_net_num(t_pb* cur_pb,
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t_pb_graph_pin* cur_pb_graph_pin);
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void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node,
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t_pb* cur_pb);
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void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_pb* cur_pb);
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void mark_one_pb_parasitic_nets(t_pb* cur_pb);
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void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,
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t_rr_node* LL_rr_node);
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boolean is_net_pi(t_net* cur_net);
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int check_consistency_logical_block_net_num(t_logical_block* lgk_blk,
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int num_inputs, int* input_net_num);
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int rr_node_drive_switch_box(t_rr_node* src_rr_node,
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t_rr_node* des_rr_node,
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int switch_box_x,
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int switch_box_y,
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int chan_side);
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void find_drive_rr_nodes_switch_box(int switch_box_x,
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int switch_box_y,
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t_rr_node* src_rr_node,
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int chan_side,
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int return_num_only,
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int* num_drive_rr_nodes,
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t_rr_node*** drive_rr_nodes,
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int* switch_index);
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int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model,
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int mux_size);
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int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model,
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enum e_sram_orgz cur_sram_orgz_type,
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int mux_size);
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int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model,
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enum e_sram_orgz cur_sram_orgz_type);
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int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model,
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enum e_sram_orgz cur_sram_orgz_type,
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int mux_size);
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int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model,
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enum e_sram_orgz cur_sram_orgz_type);
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int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model,
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enum e_sram_orgz cur_sram_orgz_type,
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int mux_size);
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int count_num_conf_bit_one_interc(t_interconnect* cur_interc,
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enum e_sram_orgz cur_sram_orgz_type);
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int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc,
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enum e_sram_orgz cur_sram_orgz_type);
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int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode,
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enum e_sram_orgz cur_sram_orgz_type);
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int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type,
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t_sram_orgz_info* cur_sram_orgz_info);
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int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
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t_sram_orgz_info* cur_sram_orgz_info);
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int rec_count_num_conf_bits_pb(t_pb* cur_pb,
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t_sram_orgz_info* cur_sram_orgz_info);
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void init_one_grid_num_conf_bits(int ix, int iy,
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t_sram_orgz_info* cur_sram_orgz_info);
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void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info);
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void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model);
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void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model);
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void zero_spice_models_routing_index_low_high(int num_spice_models,
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t_spice_model* spice_model);
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void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model);
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void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model);
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void free_spice_model_routing_index_low_high(int num_spice_models,
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t_spice_model* spice_model);
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void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type,
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t_spice_model* cur_spice_model);
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void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type,
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int num_spice_models,
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t_spice_model* spice_model);
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void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type,
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t_spice_model* cur_spice_model);
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void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type,
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int num_spice_models,
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t_spice_model* spice_model);
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void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type);
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void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type);
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void rec_count_num_iopads_pb(t_pb* cur_pb);
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void init_one_grid_num_iopads(int ix, int iy);
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void init_grids_num_iopads();
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void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type);
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void rec_count_num_mode_bits_pb(t_pb* cur_pb);
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void init_one_grid_num_mode_bits(int ix, int iy);
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void init_grids_num_mode_bits();
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void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
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boolean include_bl_wl);
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void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
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boolean is_scff);
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/* Functions to manipulate t_conf_bit and t_conf_bit_info */
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void free_conf_bit(t_conf_bit* conf_bit);
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void free_conf_bit_info(t_conf_bit_info* conf_bit_info);
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t_conf_bit_info*
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alloc_one_conf_bit_info(int index,
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t_conf_bit* sram_val,
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t_conf_bit* bl_val, t_conf_bit* wl_val,
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t_spice_model* parent_spice_model);
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t_llist*
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add_conf_bit_info_to_llist(t_llist* head, int index,
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t_conf_bit* sram_val, t_conf_bit* bl_val, t_conf_bit* wl_val,
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t_spice_model* parent_spice_model);
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void
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add_mux_scff_conf_bits_to_llist(int mux_size,
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t_sram_orgz_info* cur_sram_orgz_info,
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int num_mux_sram_bits, int* mux_sram_bits,
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t_spice_model* mux_spice_model);
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void
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add_mux_membank_conf_bits_to_llist(int mux_size,
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t_sram_orgz_info* cur_sram_orgz_info,
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int num_mux_sram_bits, int* mux_sram_bits,
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t_spice_model* mux_spice_model);
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void
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add_mux_conf_bits_to_llist(int mux_size,
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t_sram_orgz_info* cur_sram_orgz_info,
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int num_mux_sram_bits, int* mux_sram_bits,
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t_spice_model* mux_spice_model);
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void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index,
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int num_bls, int num_wls,
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int* bl_conf_bits, int* wl_conf_bits);
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void
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add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index,
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int num_sram_bits, int* sram_bits);
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void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model,
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int* num_bl_ports, t_spice_model_port*** bl_ports,
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int* num_wl_ports, t_spice_model_port*** wl_ports);
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void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model,
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int* num_blb_ports, t_spice_model_port*** blb_ports,
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int* num_wlb_ports, t_spice_model_port*** wlb_ports);
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int* decode_mode_bits(char* mode_bits, int* num_sram_bits);
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/* Useful functions for LUT decoding */
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void stats_lut_spice_mux(t_llist** muxes_head,
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t_spice_model* spice_model);
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char* complete_truth_table_line(int lut_size,
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char* input_truth_table_line);
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void configure_lut_sram_bits_per_line_rec(int** sram_bits,
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int lut_size,
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char* truth_table_line,
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int start_point);
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int* generate_lut_sram_bits(int truth_table_len,
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char** truth_table,
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int lut_size,
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int default_sram_bit_value);
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char** assign_lut_truth_table(t_logical_block* mapped_logical_block,
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int* truth_table_length);
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int get_ff_output_init_val(t_logical_block* ff_logical_block);
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int get_lut_output_init_val(t_logical_block* lut_logical_block);
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int get_logical_block_output_init_val(t_logical_block* cur_logical_block);
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/* Functions to manipulate structs of SRAM orgz */
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t_sram_orgz_info* alloc_one_sram_orgz_info();
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t_mem_bank_info* alloc_one_mem_bank_info();
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void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info);
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t_scff_info* alloc_one_scff_info();
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void free_one_scff_info(t_scff_info* scff_info);
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t_standalone_sram_info* alloc_one_standalone_sram_info();
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void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info);
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void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info,
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t_spice_model* cur_mem_model);
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void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,
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int updated_reserved_bl, int updated_reserved_wl);
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void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,
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int updated_reserved_bl, int updated_reserved_wl);
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void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,
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int* num_reserved_bl, int* num_reserved_wl);
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void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info,
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int updated_bl, int updated_wl);
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void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,
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int* num_reserved_bl, int* num_reserved_wl);
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void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info,
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int num_mem_bit);
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void init_scff_info(t_scff_info* cur_scff_info,
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t_spice_model* cur_mem_model);
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void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info,
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int num_mem_bit);
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void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info,
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t_spice_model* cur_mem_model);
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void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info,
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int num_mem_bit);
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void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,
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enum e_sram_orgz cur_sram_orgz_type,
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t_spice_model* cur_mem_model,
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int grid_nx, int grid_ny);
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void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,
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enum e_sram_orgz cur_sram_orgz_type,
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int grid_nx, int grid_ny);
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void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,
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int updated_reserved_bl, int updated_reserved_wl);
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int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info);
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void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,
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int* cur_bl, int* cur_wl);
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void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info,
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|
int new_num_mem_bit);
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|
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void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,
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int new_bl, int new_wl);
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|
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void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,
|
|
t_spice_model** mem_model_ptr);
|
|
|
|
void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char,
|
|
char cur_syntax_char, boolean cur_verilog_reserved, boolean cur_spice_reserved);
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|
|
|
void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model,
|
|
enum e_spice_model_port_type blwl_port_type,
|
|
boolean* blwl_inverted);
|
|
|
|
void init_spice_mux_arch(t_spice_model* spice_model,
|
|
t_spice_mux_arch* spice_mux_arch,
|
|
int mux_size);
|
|
|
|
int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch);
|
|
|
|
t_llist* search_mux_linked_list(t_llist* mux_head,
|
|
int mux_size,
|
|
t_spice_model* spice_model);
|
|
|
|
void check_and_add_mux_to_linked_list(t_llist** muxes_head,
|
|
int mux_size,
|
|
t_spice_model* spice_model);
|
|
|
|
void free_muxes_llist(t_llist* muxes_head);
|
|
|
|
void stats_spice_muxes_routing_arch(t_llist** muxes_head,
|
|
int num_switch,
|
|
t_switch_inf* switches,
|
|
t_spice* spice,
|
|
t_det_routing_arch* routing_arch);
|
|
|
|
void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head,
|
|
t_pb_type* cur_pb_type);
|
|
|
|
void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head,
|
|
t_pb_graph_node* cur_pb_node);
|
|
|
|
t_llist* stats_spice_muxes(int num_switch,
|
|
t_switch_inf* switches,
|
|
t_spice* spice,
|
|
t_det_routing_arch* routing_arch);
|
|
|
|
enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin);
|
|
|
|
t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin);
|
|
|
|
int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph,
|
|
int src_node,
|
|
int des_node);
|
|
|
|
t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb);
|
|
|
|
void config_spice_model_port_inv_spice_model(int num_spice_models,
|
|
t_spice_model* spice_model);
|
|
|
|
void config_spice_models_sram_port_spice_model(int num_spice_model,
|
|
t_spice_model* spice_models,
|
|
t_spice_model* default_sram_spice_model);
|
|
t_pb* get_lut_child_pb(t_pb* cur_lut_pb,
|
|
int mode_index);
|
|
|
|
t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb,
|
|
int mode_index);
|
|
|
|
int get_grid_pin_height(int grid_x, int grid_y, int pin_index);
|
|
|
|
int get_grid_pin_side(int grid_x, int grid_y, int pin_index);
|
|
|
|
void determine_sb_port_coordinator(t_sb cur_sb_info, int side,
|
|
int* port_x, int* port_y);
|
|
|
|
void init_spice_models_tb_cnt(int num_spice_models,
|
|
t_spice_model* spice_model);
|
|
|
|
void init_spice_models_grid_tb_cnt(int num_spice_models,
|
|
t_spice_model* spice_model,
|
|
int grid_x, int grid_y);
|
|
|
|
void check_spice_models_grid_tb_cnt(int num_spice_models,
|
|
t_spice_model* spice_model,
|
|
int grid_x, int grid_y,
|
|
enum e_spice_model_type spice_model_type_to_check);
|
|
|
|
boolean check_negative_variation(float avg_val,
|
|
t_spice_mc_variation_params variation_params);
|
|
|
|
boolean is_cb_exist(t_rr_type cb_type,
|
|
int cb_x, int cb_y);
|
|
|
|
int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info);
|
|
|
|
t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head,
|
|
char* subckt_file_path);
|
|
|
|
boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,
|
|
char* subckt_file_name);
|