40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
/* global parameters for FPGA-SPICE tool suites */
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extern t_spice_model* fpga_spice_sram_model;
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extern enum e_sram_orgz fpga_spice_sram_orgz_type;
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/* Input and Output Pad spice model. should be set as global */
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extern t_spice_model* fpga_spice_inpad_model;
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extern t_spice_model* fpga_spice_outpad_model;
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extern t_spice_model* fpga_spice_iopad_model;
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/* Number of configuration bits of each switch block */
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extern int** num_conf_bits_sb;
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/* Number of configuration bits of each Connection Box CHANX */
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extern int** num_conf_bits_cbx;
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/* Number of configuration bits of each Connection Box CHANY */
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extern int** num_conf_bits_cby;
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/* Prefix of global input, output and inout of a I/O pad */
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extern char* gio_input_prefix;
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extern char* gio_output_prefix;
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extern char* gio_inout_prefix;
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extern int default_signal_init_value;
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extern boolean run_parasitic_net_estimation;
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extern boolean run_testbench_load_extraction;
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/* Linked list for global ports */
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extern t_llist* global_ports_head;
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/* Linked list for verilog and spice syntax char */
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extern t_llist* reserved_syntax_char_head;
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/* Enumeration */
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enum e_pin2pin_interc_type {
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INPUT2INPUT_INTERC, OUTPUT2OUTPUT_INTERC
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};
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extern char* renaming_report_postfix;
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