63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include spice support headers*/
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#include "linkedlist.h"
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#include "fpga_spice_utils.h"
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#include "fpga_spice_backannotate_utils.h"
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#include "fpga_spice_setup.h"
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#include "spice_api.h"
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#include "syn_verilog_api.h"
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/* Top-level API of FPGA-SPICE */
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void vpr_fpga_spice_tool_suites(t_vpr_setup vpr_setup,
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t_arch Arch) {
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/* Common initializations and malloc operations */
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/* If FPGA-SPICE is not called, we should initialize the spice_models */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) {
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fpga_spice_setup(vpr_setup, &Arch);
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}
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/* Xifan TANG: SPICE Modeling, SPICE Netlist Output */
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) {
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vpr_print_spice_netlists(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);
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}
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/* Xifan TANG: Synthesizable verilog dumping */
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if (vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) {
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vpr_dump_syn_verilog(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);
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}
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/* Free */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) {
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/* Free all the backannotation containing post routing information */
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free_backannotate_vpr_post_route_info();
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/* TODO: free other linked lists ! */
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fpga_spice_free(&Arch);
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}
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return;
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}
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