261 lines
10 KiB
ReStructuredText
261 lines
10 KiB
ReStructuredText
.. _openfpga_commands:
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Commands
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--------
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As OpenFPGA integrates various tools, the commands are categorized into different classes:
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Basic Commands
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~~~~~~~~~~~~~~
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.. option:: help
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Show help desk to list all the available commands
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.. option:: exit
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Exit OpenFPGA shell
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VPR
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~~~
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.. option:: vpr
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OpenFPGA allows users to call ``vpr`` in the standard way as documented in vtr project.
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Setup OpenFPGA
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~~~~~~~~~~~~~~
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.. option:: read_openfpga_arch
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Read the XML architecture file required by OpenFPGA
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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.. option:: write_openfpga_arch
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Write the OpenFPGA XML architecture file to a file
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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.. option:: link_openfpga_arch
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Annotate the OpenFPGA architecture to VPR data base
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- ``--activity_file`` Specify the signal activity file
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- ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
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- ``--verbose`` Show verbose log
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.. option:: write_gsb_to_xml
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Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
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- ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
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- ``--verbose`` Show verbose log
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.. note:: This command is used to help users to study the difference between GSBs
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.. option:: check_netlist_naming_conflict
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Check and correct any naming conflicts in the BLIF netlist
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This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--fix`` Apply fix-up to the names that violate the syntax
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- ``--report <.xml>`` Report the naming fix-up to a log file
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.. option:: pb_pin_fixup
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Apply fix-up to clustering nets based on routing results
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This is strongly recommended. Otherwise, the bitstream generation may be wrong
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--verbose`` Show verbose log
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.. option:: lut_truth_table_fixup
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Apply fix-up to Look-Up Table truth tables based on packing results
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--verbose`` Show verbose log
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.. option:: build_fabric
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Build the module graph.
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- ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
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- ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
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- ``--verbose`` Show verbose log
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.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
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.. option:: write_fabric_hierarchy
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Write the hierarchy of FPGA fabric graph to a plain-text file
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- ``--file`` or ``-f`` Specify the file name to write the hierarchy.
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- ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
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- ``--verbose`` Show verbose log
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.. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
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FPGA-Bitstream
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~~~~~~~~~~~~~~
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.. option:: repack
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Repack the netlist to physical pbs
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This must be done before bitstream generator and testbench generation
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Strongly recommend it is done after all the fix-up have been applied
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- ``--verbose`` Show verbose log
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.. option:: build_architecture_bitstream
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Decode VPR implementing results to an fabric-independent bitstream database
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- ``--file`` or ``-f`` Output the fabric-independent bitstream to an XML file
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- ``--verbose`` Show verbose log
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.. option:: build_fabric_bitstream
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Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric
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- ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
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- ``--verbose`` Show verbose log
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FPGA-Verilog
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~~~~~~~~~~~~
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.. option:: write_fabric_verilog
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Write the Verilog netlist for FPGA fabric based on module graph
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- ``--file`` or ``-f`` Specify the output directory for the Verilog netlists
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- ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
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- ``--include_timing`` Output timing information to Verilog netlists for primitive modules
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- ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules
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- ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept
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- ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
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- ``--verbose`` Show verbose log
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.. option:: write_verilog_testbench
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Write the Verilog testbench for FPGA fabric
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- ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
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- ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
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- ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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- ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification
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- ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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- ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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- ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
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FPGA-SDC
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~~~~~~~~
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.. option:: write_pnr_sdc
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Write the SDC files for PnR backend
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- ``--file`` or ``-f`` Specify the output directory for SDC files
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- ``--hierarchical`` Output SDC files without full path in hierarchy
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- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
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- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
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- ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks.
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.. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
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- ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
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- ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
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.. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
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- ``--constrain_grid`` Constrain all the grids of FPGA fabric
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- ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric
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- ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric
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- ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric
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- ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric
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- ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
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- ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
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.. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
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- ``--verbose`` Enable verbose output
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.. option:: write_configuration_chain_sdc
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Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained!
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- ``--file`` or ``-f`` Specify the output SDC file
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- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
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- ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
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- ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
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.. note::
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Only applicable when configuration chain is used as configuration protocol
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.. option:: write_sdc_disable_timing_configure_ports
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Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers
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- ``--file`` or ``-f`` Specify the output SDC file
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- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
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- ``--verbose`` Show verbose log
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.. option:: write_analysis_sdc
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Write the SDC to run timing analysis for a mapped FPGA fabric
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- ``--file`` or ``-f`` Specify the output directory for SDC files
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- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
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- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
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