tangxifan eeb1bd6662 [core] fixed some bugs		2023-09-17 23:16:15 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[test] deploy new tests	2023-07-08 21:52:16 -07:00
misc	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
openfpga_arch	[test] added a new test case to validate the support on different wire segment distribution on X and Y	2023-08-22 11:20:14 -07:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] add a new test to validate renaming rules	2023-09-17 13:29:12 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	[test] add a new test to validate renaming on fpga top/core modules	2023-09-17 17:38:37 -07:00
scripts	[test] reworking adder mapping flow to validate carry chain mapping	2023-06-20 16:57:08 -07:00
tasks	[core] fixed some bugs	2023-09-17 23:16:15 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[test] added a new test case to validate the support on different wire segment distribution on X and Y	2023-08-22 11:20:14 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00