51 lines
1.8 KiB
ReStructuredText
51 lines
1.8 KiB
ReStructuredText
.. _file_formats_tile_config_file:
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Tile Organization (.xml)
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------------------------
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The XML-based description language is used to describe how each tile is composed.
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For example, what programmable blocks, connection blocks and switch blocks should be included.
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Using the description language, users can customize the tiles of an FPGA fabric, as detailed as each component in each tile.
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Under the root node ``<tiles>``, the detailes of tile organization can be described.
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.. code-block:: xml
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<tiles style="<string>"/>
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</tiles>
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Syntax
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``````
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Detailed syntax are presented as follows.
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.. option:: style="<string>"
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Specify the style of tile organization. Can be [``top_left`` | ``top_right`` | ``bottom_left`` | ``bottom_right`` | ``custom``]
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.. warning:: Currently, only ``top_left`` and ``bottom_left`` are supported!
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The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
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The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
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.. _fig_tile_style_top_left:
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.. figure:: ./figures/tile_style_top_left.png
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:width: 100%
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:alt: An example of top-left style of tile
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An example of top-left style of a tile in FPGA fabric
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.. _fig_tile_style_bottom_left:
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.. figure:: ./figures/tile_style_bottom_left.png
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:width: 100%
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:alt: An example of bottom-left style of tile
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An example of bottom-left style of a tile in FPGA fabric
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