43 lines
1.4 KiB
ReStructuredText
43 lines
1.4 KiB
ReStructuredText
.. _file_formats_module_naming_file:
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Fabric Module Naming (.xml)
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---------------------------
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The XML-based description language is used to describe module names for an FPGA fabric, including:
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- the built-in name or default name for each module when building an FPGA fabric
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- the customized name which is given by users for each module, in place of the built-in names
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Using the description language, users can customize the name for each module in an FPGA fabric, excluding testbenches.
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Under the root node ``<module_names>``, naming rules can be defined line-by-line through syntax ``<module_name>``.
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.. code-block:: xml
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<module_names>
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<module_name default="<string>" given="<string>"/>
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</module_names>
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.. note:: If you do not need to rename a module of an FPGA fabric, there is no need to define it explicitly in the naming rules. OpenFPGA can infer it.
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Syntax
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``````
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Detailed syntax are presented as follows.
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.. option:: default="<string>"
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Define the default or built-in name of a module. This follows fixed naming rules of OpenFPGA. Suggest to run command :ref:`openfpga_setup_commands_write_module_naming_rules` to obtain an initial version for your fabric. For example,
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.. code-block:: xml
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default="cbx_1__2_"
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.. option:: given="<string>"
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Define the customized name of a module, this is the final name will appear in netlists. For example,
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.. code-block:: xml
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given="cbx_corner_left_bottom"
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