OpenFPGA

History

AurelienUoU 555570c15e Update Yosys from version 0.7 to version 0.8		2019-05-23 16:03:08 -06:00
..
.gitignore	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
README	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
cmos_cells.lib	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
cmos_cells.sp	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
cmos_cells.v	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
cmos_cells_digital.sp	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
counter.v	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
counter.ys	Update Yosys from version 0.7 to version 0.8	2019-05-23 16:03:08 -06:00
counter_digital.ys	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
counter_tb.gtkw	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
counter_tb.v	Update Yosys from version 0.7 to version 0.8	2019-05-23 16:03:08 -06:00
testbench.sh	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
testbench.sp	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
testbench_digital.sh	Update Yosys from version 0.7 to version 0.8	2019-05-23 16:03:08 -06:00
testbench_digital.sp	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00

README

In this directory contains an example for generating a spice output using two
different spice modes, normal analog transient simulation and event-driven
digital simulation as supported by ngspice xspice sub-module.

Each test bench can be run separately by either running:

- testbench.sh, to start analog simulation or
- testbench_digital.sh for mixed-signal digital simulation.

The later case also includes pure verilog simulation using the iverilog
and gtkwave for comparison.