51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/03/2021 03:25:29 PM
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// Design Name:
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// Module Name: clk_divider
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// Uncomment if using Vivado to synthesize the design. This will enable the initial block
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// If using Yosys, initial blocks are not supported, and cannot be included.
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// `define VIVADO_SYNTHESIS
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module clock_divider (
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input clk_in,
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output reg clk_out
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);
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parameter CLK_DIVIDER_SIZE=8;
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reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
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`ifdef VIVADO_SYNTHESIS
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initial begin
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clkdiv_counter <= 0;
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clk_out <= 0;
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end
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`endif
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// Divide pl_clk (50MHz) to 1MHz
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always @(posedge clk_in) begin
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if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin
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clk_out <= ~clk_out;
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end
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clkdiv_counter <= clkdiv_counter +1;
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end
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endmodule
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