98 lines
3.6 KiB
Verilog
98 lines
3.6 KiB
Verilog
// FIFO buffer implemented with synchronous dual-port block ram
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// Reference:
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// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
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module fifo
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#( parameter ADDRESS_WIDTH = 4, // number of words in ram
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DATA_WIDTH = 4 // number of bits in word
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)
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// IO ports
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(
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input wire clk, reset,
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input wire read, write,
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input wire [DATA_WIDTH-1:0] write_data,
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output wire empty, full,
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output wire [DATA_WIDTH-1:0] read_data
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);
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// internal signal declarations
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reg [ADDRESS_WIDTH-1:0] write_address_reg, write_address_next, write_address_after;
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reg [ADDRESS_WIDTH-1:0] read_address_reg, read_address_next, read_address_after;
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reg full_reg, empty_reg, full_next, empty_next;
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wire write_en;
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// write enable is asserted when write input is asserted and FIFO isn't full
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assign write_en = write & ~full_reg;
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// instantiate synchronous block ram
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sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram
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(.clk(clk), .write_en(write_en), .write_address(write_address_reg),
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.read_address(read_address_reg), .write_data_in(write_data),
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.write_data_out(), .read_data_out(read_data));
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// register for address pointers, full/empty status
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always @(posedge clk, posedge reset)
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if (reset)
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begin
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write_address_reg <= 0;
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read_address_reg <= 0;
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full_reg <= 1'b0;
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empty_reg <= 1'b1;
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end
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else
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begin
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write_address_reg <= write_address_next;
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read_address_reg <= read_address_next;
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full_reg <= full_next;
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empty_reg <= empty_next;
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end
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// next-state logic for address index values after read/write operations
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always @*
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begin
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write_address_after = write_address_reg + 1;
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read_address_after = read_address_reg + 1;
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end
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// next-state logic for address pointers
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always @*
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begin
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// defaults
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write_address_next = write_address_reg;
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read_address_next = read_address_reg;
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full_next = full_reg;
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empty_next = empty_reg;
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// if read input asserted and FIFO isn't empty
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if(read && ~empty_reg && ~write)
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begin
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read_address_next = read_address_after; // read address moves forward
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full_next = 1'b0; // FIFO isn't full if a read occured
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if (read_address_after == write_address_reg) // if read address caught up with write address,
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empty_next = 1'b1; // FIFO is empty
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end
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// if write input asserted and FIFO isn't full
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else if(write && ~full_reg && ~read)
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begin
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write_address_next = write_address_after; // write address moves forward
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empty_next = 1'b0; // FIFO isn't empty if write occured
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if (write_address_after == read_address_reg) // if write address caught up with read address
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full_next = 1'b1; // FIFO is full
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end
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// if write and read are asserted
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else if(write && read)
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begin
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write_address_next = write_address_after; // write address moves forward
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read_address_next = read_address_after; // read address moves forward
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end
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end
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// assign full/empty status to output ports
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assign full = full_reg;
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assign empty = empty_reg;
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endmodule
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