29 lines
543 B
Verilog
29 lines
543 B
Verilog
/////////////////////////////////////////
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// Functionality: Use clock to gate the output of an AND2 gate
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// This is to test if LUTs can be mapped as wires
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module clk_gate(
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rst_i,
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clk_i,
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data_i,
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data_o);
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input wire rst_i;
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input wire clk_i;
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input wire data_i;
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output wire data_o;
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reg q;
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always @(posedge clk_i) begin
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if (rst_i) begin
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q <= 0;
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end else begin
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q <= 1;
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end
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end
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assign data_o = data_i & q;
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endmodule
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