OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif

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# Use a FF with constant input to connect a clock signal (frequency divided by 2) from a global network to datapath
# Use an external signal to enable the clock signal
.model clk_gate
.inputs rst_i clk_i data_i
.outputs data_o
.names $true
1
.names $true ff_i
1 1
.names ff_o data_i data_o
11 1
.subckt dffr D=ff_i Q=ff_o C=clk_i R=rst_i
.end