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OpenFPGA
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OpenFPGA/openfpga
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tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
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src [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00