68 lines
1.9 KiB
Verilog
68 lines
1.9 KiB
Verilog
// Arithmetic units: adder
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// Adapt from: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/0ad1af26a29243a9e76379943d735e119dcd0cc6/ql-qlf-plugin/qlf_k6n10/cells_sim.v
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// Many thanks to F4PGA for their contribution
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(* techmap_celltype = "$alu" *)
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module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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output [Y_WIDTH-1:0] CO;
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wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH: 0 ] CARRY;
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assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
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// Due to VPR limitations regarding IO connexion to carry chain,
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// we generate the carry chain input signal using an intermediate adder
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// since we can connect a & b from io pads, but not cin & cout
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generate
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adder intermediate_adder (
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.cin ( ),
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.cout (CARRY[0]),
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.a (CI ),
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.b (CI ),
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.sumout ( )
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);
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adder first_adder (
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.cin (CARRY[0]),
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.cout (CARRY[1]),
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.a (AA[0] ),
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.b (BB[0] ),
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.sumout (Y[0] )
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);
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endgenerate
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genvar i;
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generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
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adder my_adder (
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.cin (CARRY[i] ),
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.cout (CARRY[i+1]),
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.a (AA[i] ),
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.b (BB[i] ),
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.sumout (Y[i] )
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);
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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