165 lines
3.5 KiB
Verilog
165 lines
3.5 KiB
Verilog
//////////////////////////
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// arithmetic //
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//////////////////////////
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module \$alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH:0] X, Y;
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input CI, BI;
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output [Y_WIDTH:0] CO;
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wire [Y_WIDTH-1:0] AA, BB;
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wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
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generate
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if (A_SIGNED && B_SIGNED) begin:BLOCK1
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assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
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end else begin:BLOCK2
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assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
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end
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endgenerate
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wire [Y_WIDTH: 0 ] CARRY;
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assign CARRY[0] = CI;
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genvar i;
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generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
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adder my_adder (
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.cin (CARRY[i]),
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.cout (CARRY[i+1]),
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.a (AA[i]),
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.b (BB[i]),
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.sumout (Y[i])
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);
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end endgenerate
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generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
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assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
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end else begin:gen5
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adder my_adder (
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.cin (CARRY[Y_WIDTH - 1]),
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.cout (CARRY[Y_WIDTH]),
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.a (1'b0),
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.b (1'b0),
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.sumout (Y[Y_WIDTH -1])
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);
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end
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endgenerate
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endmodule
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//---------------------------------------------------------
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module \$fa (A, B, C, X, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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input C;
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output [Y_WIDTH:0] X, Y;
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wire [Y_WIDTH-1:0] AA, BB;
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wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
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generate
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if (A_SIGNED && B_SIGNED) begin:BLOCK1
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assign AA = $signed(A), BB = $signed(B);
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end else begin:BLOCK2
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assign AA = $unsigned(A), BB = $unsigned(B);
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end
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endgenerate
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wire [Y_WIDTH: 0 ] CARRY;
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assign CARRY[0] = C;
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genvar i;
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generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
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adder my_adder (
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.cin (CARRY[i]),
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.cout (CARRY[i+1]),
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.a (AA[i]),
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.b (BB[i]),
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.sumout (Y[i])
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);
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end endgenerate
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generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
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assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
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end else begin:gen5
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adder my_adder (
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.cin (CARRY[Y_WIDTH - 1]),
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.cout (CARRY[Y_WIDTH]),
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.a (1'b0),
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.b (1'b0),
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.sumout (Y[Y_WIDTH -1])
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);
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end
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endgenerate
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endmodule
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//---------------------------------------------------------
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module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH:0] Y;
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wire [Y_WIDTH-1:0] AA, BB;
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wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
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generate
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if (A_SIGNED && B_SIGNED) begin:BLOCK1
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assign AA = $signed(A), BB = $signed(B);
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end else begin:BLOCK2
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assign AA = $unsigned(A), BB = $unsigned(B);
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end
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endgenerate
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wire [Y_WIDTH: 0 ] CARRY;
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assign CARRY[0] = 1'b0;
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genvar i;
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generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
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adder my_adder (
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.cin (CARRY[i]),
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.cout (CARRY[i+1]),
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.a (AA[i]),
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.b (BB[i]),
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.sumout (Y[i])
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);
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end endgenerate
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generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
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assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
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end else begin:gen5
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adder my_adder (
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.cin (CARRY[Y_WIDTH - 1]),
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.cout (CARRY[Y_WIDTH]),
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.a (1'b0),
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.b (1'b0),
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.sumout (Y[Y_WIDTH -1])
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);
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end
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endgenerate
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endmodule
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