57 lines
1.2 KiB
ReStructuredText
57 lines
1.2 KiB
ReStructuredText
.. OpenFPGA documentation master file, created by
|
|
sphinx-quickstart on Thu Sep 13 12:15:14 2018.
|
|
You can adapt this file completely to your liking, but it should at least
|
|
contain the root `toctree` directive.
|
|
|
|
Welcome to OpenFPGA's documentation!
|
|
====================================
|
|
|
|
.. toctree::
|
|
:maxdepth: 2
|
|
:caption: Overview
|
|
|
|
overview/index
|
|
|
|
.. toctree::
|
|
:maxdepth: 2
|
|
:caption: Tutorials
|
|
|
|
tutorials/index
|
|
|
|
.. toctree::
|
|
:maxdepth: 2
|
|
:caption: User Manual
|
|
|
|
manual/index
|
|
|
|
.. toctree::
|
|
:maxdepth: 2
|
|
:caption: Developers Manual
|
|
|
|
dev_manual/index
|
|
|
|
.. toctree::
|
|
:maxdepth: 2
|
|
:caption: Appendix
|
|
|
|
appendix/index
|
|
|
|
For more information on the VTR see vtr_doc_ or vtr_github_
|
|
|
|
For more information on the Yosys see yosys_doc_ or yosys_github_
|
|
|
|
For more information on the original FPGA architecture description language see xml_vtr_
|
|
|
|
Indices and tables
|
|
==================
|
|
|
|
* :ref:`genindex`
|
|
* :ref:`modindex`
|
|
* :ref:`search`
|
|
|
|
.. _vtr_doc: https://docs.verilogtorouting.org/en/latest/
|
|
.. _vtr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
|
|
.. _yosys_doc: http://www.clifford.at/yosys/
|
|
.. _yosys_github: https://github.com/YosysHQ/yosys
|
|
.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/
|